INTEGRATED CIRCUITS
DATA SHEET
SAA5244A
Integrated VIP and teletext decoder
(IVT1.1)
Product specification
File under Integrated Circuits, IC02
March 1992
Philips Semiconductors
Product specification
Integrated VIP and teletext decoder
(IVT1.1)
FEATURES
•
Complete teletext decoder including page memory in a
single 40-pin DIL package
•
Single +5 V power supply
•
Digital data slicer and display clock phase-locked loop
reduces peripheral components to a minimum
•
Both video and scan related synchronization modes are
supported
•
On board single page memory including extension
packets for FASTEXT
•
Single page acquisition system
•
RGB interface to standard colour decoder ICs, push-pull
output drive
•
Data capture performance similar to SAA5231 (VIP2)
•
Simple software control via I
2
C-bus
•
Option for five national languages
•
32 supplementary characters for on-screen displays
•
Optional storage of packet 24 in the display memory
•
Page links in packets 27 and 8/30 are Hamming
decoded
•
Separate text and video signal quality detectors,
625/525 video status and language version all readable
via I
2
C-bus
•
Automatic ODD/EVEN output control with manual
override
•
Control of display PLL free-run and rolling header via
I
2
C-bus
•
VCS to SCS mode for stable 525 line status display
ORDERING INFORMATION
EXTENDED TYPE
NUMBER
SAA5244AP
SAA5244AGP
Notes
1. SOT129-1; 1996 December 16.
2. SOT205-1; 1996 December 16.
PACKAGE
PINS
40
44
PIN POSITION
DIL
QFP
MATERIAL
plastic
plastic
DESCRIPTION
SAA5244A
The Integrated VIP and Teletext (IVT1.1) is a teletext
decoder (contained within a single-chip package) for
decoding 625-line based World System Teletext
transmissions. The teletext decoder hardware is based on
a reduced function version of the device SAA5246
(IVT1.0).
The Video Input Processor (VIP) section of the device
uses mixed analog and digital designs for the data slicer
and the display clock phase-locked loop functions. As a
result the number of external components is greatly
reduced and no critical or adjustable components are
required. A single page static RAM is incorporated in the
device thereby giving a genuine single-chip teletext
decoder device.
CODE
SOT129
(1)
SOT205A
(2)
March 1992
2
Philips Semiconductors
Product specification
Integrated VIP and teletext decoder
(IVT1.1)
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
V
syn
V
vid
f
XTAL
T
amb
supply current
sync amplitude
video amplitude
crystal frequency
operating ambient temperature range
PARAMETER
positive supply voltage
4.5
−
0.1
0.7
−
−20
MIN.
5
74
0.3
1
27
−
TYP.
SAA5244A
MAX.
5.5
148
0.6
1.4
−
70
V
UNIT
mA
V
V
MHz
°C
March 1992
3
Philips Semiconductors
Product specification
Integrated VIP and teletext decoder
(IVT1.1)
SAA5244A
Y
BLAN
COR RGBREF RGB ODD / EVEN
handbook, full pagewidth
23
19
21
18
15-17
22
DISPLAY
PAGE
MEMORY
DATA
SLICER
AND
CLOCK
REGENERATOR
TELETEXT
ACQUISITION
AND
DECODING
25
I C-BUS
INTERFACE
DCVBS
1
V SS
5
ANALOG
TO
DIGITAL
CONVERTER
REF
6
10
2
SDA
SCL
24
VDD
VDD
VSS
SAA5244A
TIMING
CHAIN
14
20
OSCOUT
OSCIN
2
3
CRYSTAL
OSCILLATOR
INPUT
CLAMP
AND SYNC
SEPARATOR
DISPLAY
CLOCK
PHASE
LOCKED
LOOP
11
13
12
4
7
9
8
MLA228 - 1
OSCGND
BLACK IREF CVBS POL VCR / FFB STTV / LFB
Fig.1 Block diagram for SOT129 (DIL40) package.
March 1992
4
Philips Semiconductors
Product specification
Integrated VIP and teletext decoder
(IVT1.1)
PINNING
SYMBOL
V
DD
OSCOUT
OSCIN
OSCGND
V
SS
REF−
REF+
BLACK
CVBS
IREF
V
DD
POL
STTV/LFB
VCR/FFB
V
SS
R
G
B
RGBREF
BLAN
V
SS
COR
SOT129 SOT205A
1
2
3
4
5
−
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
18
19
20
21
22
−
23
24
25
26
27
28
29
32
33
34
35
36
37
38
39
40
+5 V supply
27 MHz crystal oscillator output
27 MHz crystal oscillator input
0 V crystal oscillator ground
0 V ground
DESCRIPTION
SAA5244A
negative reference voltage for the ADC. The pin should be connected to 0 V
positive reference voltage for the ADC. The pin should be connected to +5 V
video black level storage pin, connected to ground via a 100 nF capacitor
composite video input pin. A positive-going 1 V (peak-to-peak) input is required,
connected via a 100 nF capacitor
reference current input pin, connected to ground via a 27 kΩ resistor
+5 V supply
STTV/LFB/FFB polarity selection pin
sync to TV output pin/line flyback input pin. Function controlled by an internal
register bit (scan sync mode)
PLL time constant switch/field flyback input pin. Function controlled by an
internal register bit (scan sync mode)
0 V ground
dot rate character output of the RED colour information
dot rate character output of the GREEN colour information
dot rate character output of the BLUE colour information
input DC voltage to define the output high level on the RGB pins
dot rate fast blanking output
0 V ground
programmable output to provide contrast reduction of the TV picture for mixed
text and picture displays or when viewing newsflash/subtitle pages; open drain
output
25 Hz output synchronized with the CVBS input’s field sync pulses to produce a
non-interlaced display by adjustment of the vertical deflection currents
dot rate character output of teletext foreground colour information open drain
output
serial clock input for the I
2
C-bus. It can still be driven during power-down of the
device
serial data port for the I
2
C-bus; open drain output. It can still be driven during
power-down of the device
not connected
internally connected. Must be left open-circuit in application
ODD/EVEN
Y
SCL
SDA
n.c.
i.c.
22
23
24
25
−
41
42
43
44
4 to 7
30, 31
26 to 40 1 to 3
8 to 17
March 1992
5
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