INTEGRATED CIRCUITS
DATA SHEET
SAA1101
Universal sync generator (USG)
Product specification
File under Integrated Circuits, IC02
January 1990
Philips Semiconductors
Product specification
Universal sync generator (USG)
FEATURES
•
Programmable to seven standards
•
Additional outputs to simplify signal processing
•
Can be synchronized to an external sync. signal
•
Option to select the 524/624 line mode instead of the 525/625 line mode
•
Lock from subcarrier to line frequency
GENERAL DESCRIPTION
SAA1101
The SAA1101 is a Universal Sync Generator (USG) and is designed for application in video sources such as cameras,
film scanners, video generators and associated apparatus. The circuit can be considered as a successor to the SAA1043
sync generator and the SAA1044 subcarrier coupling IC.
QUICK REFERENCE DATA
SYMBOL
V
DD
I
DD
f
OSC
quiescent supply current
clock oscillator frequency
PARAMETER
supply voltage range (pin 28)
MIN.
4.5
−
−
MAX.
5.5
10
24
V
µA
MHz
UNIT
ORDERING AND PACKAGE INFORMATION
EXTENDED
TYPE NUMBER
SAA1101P
SAA1101T
Notes
1. SOT117-1; 1996 December 02.
2. SOT136-1; 1996 December 02.
28
28
PACKAGE
PINS
DIL
SO28
PIN POSITION
MATERIAL
plastic
plastic
CODE
SOT117
(1)
SOT136A
(2)
January 1990
2
k, full pagewidth
January 1990
NORM
23
13
SI
3
24
160fH
CS
CB
BK
ID
HD
VD
WMP
CLP
12
RR
LINE
DIVIDER
17
16
15
22
21
20
19
40fH
RESET
PULSE
SHAPER
COMBINING
LOGIC
VERTICAL
DIVIDER
2fH
18
ADDITION/
SUPPRESSION
LOGIC
CS0 CS1 CLO
Philips Semiconductors
4
PRESCALER
OSCI
5
Universal sync generator (USG)
OSCO
6
X
STANDARD
PROGRAMMED
DIVIDER
VERTICAL
LOCK
VERTICAL
DETECTION
∆f
SUBCARRIER
SUBTRACTION
Href
HRI
fs
− ∆f
SUBCARRIER
DIVIDER
fH
fH
HORIZONTAL
DETECTION
25
7
VLE
Y
26
Z
27
3
LOCK MODE
SELECTION
PHASE
DETECTION
28
VSS
14
8
PH
9
10
LM1 LM0
11
ECS
FSI
1
fs
FSO
2
SAA1101
MGH191
VDD
SAA1101
Product specification
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Universal sync generator (USG)
PINNING
SYMBOL PIN
fpage
SAA1101
DESCRIPTION
subcarrier oscillator input, where f
max
= 5 MHz
subcarrier oscillator output
clock frequency selection - CMOS input
clock frequency selection - CMOS input
clock oscillator input, where f
max
= 24 MHz
clock oscillator output
vertical in-lock enable - CMOS input
phase detector output - 3-state output
lock mode selection - CMOS input
lock mode selection - CMOS input
external composite sync. signal - CMOS Schmitt-trigger
input
frame reset - CMOS Schmitt-trigger input
set identification, used to set the correct field sequence in
PAL-mode. The correction (inversion of fH2) is done at the
left-hand slope of the SI-pulse. Minimum pulse width is
800 ns. CMOS Schmitt-trigger input.
ground
identification - push-pull output
burst key (PAL/NTSC), chroma-blanking (SECAM) -
push-pull output
composite blanking - push-pull output
composite sync. - push-pull output
clamp pulse - push-pull output
white measurement pulse-3-state output
vertical drive pulse - push-pull output
horizontal drive pulse - push-pull output
used with X, Y and Z to select TV system; NORM = 0,
625/525 line mode (standard);
NORM = 1, 624/524 line mode - CMOS input
clock output - push-pull output
TV system selection input - CMOS input
TV system selection input - CMOS input
TV system selection input - CMOS input
voltage supply
FSI 1
FSO 2
CS1 3
CS0 4
OSCI 5
OSCO 6
VLE 7
28 VDD
27 Z
26 Y
25 X
24 CLO
23 NORM
22 HD
FSI
FSO
CS1
CS0
OSCI
OSCO
VLE
PH
LM1
LM0
ECS
RR
SI
1
2
3
4
5
6
7
8
9
10
11
12
13
SAA1101
PH 8
LM1 9
LM0 10
ECS 11
RR 12
SI 13
VSS 14
MGH190
21 VD
20 WMP
19 CLP
18 CS
17 CB
16 BK
15 ID
V
SS
ID
BK
CB
14
15
16
17
18
19
20
21
22
23
Fig.2
Pinning configuration;
SOT117.
FUNCTIONAL DESCRIPTION
Generation of pulses
Generation of standard pulses such
as sync, blanking and burst for TV
systems: PAL B/G, PALN, PALM,
SECAM and NTSC. In addition a
number of non-standard pulses have
been supplied to simplify signal
processing. These signals include -
horizontal drive, vertical drive, clamp
pulse, identification etc. It is possible
to select the 524/624 line mode
instead of the 525/625 line mode for
all the above TV systems for
applications such as robotics, games
and computers.
CS
CLP
WMP
VD
HD
NORM
CLO
X
Y
Z
V
DD
24
25
26
27
28
January 1990
4
Philips Semiconductors
Product specification
Universal sync generator (USG)
Lock modes
The USG offers four lock modes:
•
Lock from the subcarrier
•
Slow sync. lock, external H
ref
•
Slow sync. lock, internal H
ref
•
Fast sync. lock, internal H
ref
LOCK FROM SUBCARRIER
Lock from subcarrier to the line frequency for the above
mentioned TV systems is given below; the horizontal
frequency (f
H
) = 15.625 kHz for 625 line systems and
15.734264 kHz for 525 line systems.
0
0
1
1
SECAM (1 and 2)
PALN
NTSC (1 and 2)
PALM
PAL B/G
282f
H
229.2516f
H
227.5f
H
227.25f
H
283.7516f
H
LM0
0
1
0
1
LM1
SAA1101
subcarrier input is, in this case, used as an external
input for the horizontal reference, see Fig.3(d).
SELECTION OF LOCK MODE
Lock mode is selected using the inputs LM0 and LM1 as
illustrated in the Table below.
SELECTION
lock to subcarrier
slow sync. lock external H
ref
slow sync. lock internal H
ref
fast sync. lock internal H
ref
These relationships are obtained by the use of a phase
locked loop and the internal programmed divider chain,
see Fig.3(a).
LOCK TO AN EXTERNAL SIGNAL SOURCE
The following methods can be used to lock to an external
signal source:
1. Sync. lock slow; the line frequency is locked to an
external signal. The line and frame information are
extracted from the external sync. signal and used
separately in the lock system. The line information is
used in a phase-locked loop where external and
internal line frequencies are compared by the same
phase detector as is used for the subcarrier lock. The
external frame information is compared with the
internal frame in a slow lock system; mismatch of
internal and external frames will result in the addition
or suppression of one line depending on the direction
of the fault. The maximum lock time for frame lock is
6.25 s, see Fig.3(b).
2. Sync. lock fast. A fast lock of frames is possible with a
frame reset which is extracted out of the incoming
external sync. signal, see Fig.3(c).
3. Sync. lock with external reference. Lock of an external
sync. signal to the line frequency with an external line
reference to make possible a shifted lock. The
January 1990
5
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