INTEGRATED CIRCUITS
74ALS112A
Dual J-K negative edge-triggered flip-flop
Product specification
IC05 Data Handbook
1996 June 27
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
DESCRIPTION
The 74ALS112A, dual negative edge-triggered JK-type flip-flop
features individual J, K, clock (CPn), set (SD), and reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the function table regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and the flip-flop will perform
according to the function table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
TYPICAL
SUPPLY CURRENT
(TOTAL)
3.0mA
PIN CONFIGURATION
CP0
K0
J0
SD0
Q0
Q0
Q1
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RD0
RD1
CP1
K1
J1
SD1
Q1
SF00103
TYPE
74ALS112A
TYPICAL
f
MAX
50MHz
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
74ALS112AN
74ALS112AD
DRAWING
NUMBER
16-pin plastic DIP
16-pin plastic SO
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
CP0, CP1
J0, J1
K0, K1
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
DESCRIPTION
Clock Pulse input (active falling edge)
J inputs
K inputs
Set inputs (active-Low)
Reset inputs (active-Low)
Data outputs
74ALS (U.L.)
HIGH/LOW
1.0/1.0
1.0/2.0
1.0/2.0
1.0/2.0
1.0/2.0
20/80
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
20µA/0.2mA
0.4mA/8mA
NOTE:
One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
3
11
2 12
IEC/IEEE SYMBOL
3
1
1
4
15
13
10
14
J0
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
11
13
12
14
10
V
CC
= Pin 16
GND = Pin 8
5
6
9
7
J1
K0 K1
2
15
4
1J
C1
1K
R
S
5
6
2J
C2
2K
R
S
7
9
SF00104
SF00105
1996 Jun 27
2
853-1846 16995
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
LOGIC DIAGRAM
5, 9
Qn
6, 7
Qn
4, 10
SDn
2, 12
Kn
15, 14
RDn
3, 11
Jn
V
CC
= Pin 16
GND = Pin 8
1, 13
CPn
SF00106
FUNCTION TABLE
INPUTS
SD
L
H
L
H
H
H
H
H
RD
H
L
L
H
H
H
H
H
CP
X
X
X
↓
↓
↓
↓
H
J
X
X
X
h
h
l
l
X
K
X
X
X
h
l
h
l
X
OUTPUTS
OPERATING MODE
Q
H
L
H*
q
H
L
q
q
Q
L
H
H*
q
L
H
q
q
Asynchronous Set
Asynchronous Reset
Undetermined *
Toggle
Load “1” (Set)
Load “0” (Reset)
Hold “no change”
Hold “no change”
H = High voltage level
h = High state must be present one setup time prior to High-to-Low clock transition
L = Low voltage level
l = Low state must be present one setup time prior to High-to-Low clock transition
q = Lower case indicate the state of the referenced output prior to the High-to-Low clock transition
X = Don’t care
↓
= High-to-Low clock transition
* = Both outputs will be High while both SD and RD are Low, but the output states are unpredictable if SD and RD go High simultaneously
Asynchronous inputs: Low input to SD sets Q to High level, Low input to RD sets Q to Low level. Set and reset are independent of clock.
Simultaneous Low on both SD and RD makes both Q and Q High.
1996 Jun 27
3
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
16
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
2.0
0.8
–18
–0.4
8
+70
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
OH
V
O
OL
V
IK
I
I
I
IH
I
IL
I
O
I
CC
PARAMETER
High-level output voltage
TEST CONDITIONS
1
MIN
V
CC
=
±10%,
V
IL
= MAX, V
IH
= MIN
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN
Input clamp voltage
Input current at maximum input voltage
High-level input current
CPn
Low-level input current
Output current
3
Supply current (total)
SDn, RDn,
Jn, Kn
V
CC
= MAX, V
I
= 0.4V
V
CC
= MAX, V
O
= 2.25V
V
CC
= MAX
–30
2.5
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
I
OH
= –0.4mA
I
OL
= 4mA
I
OL
= 8mA
V
CC
– 2
0.25
0.35
–0.73
0.40
0.50
–1.5
0.1
20
–0.1
–0.2
–112
4.5
LIMITS
TYP
2
UNIT
MAX
V
V
V
V
mA
µA
mA
mA
mA
mA
Low-level
Low level output voltage
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. The output conditions have been chosen to produce a current that closely approximates one half of the true short–circuit output current, I
OS
.
1996 Jun 27
4
Philips Semiconductors
Product specification
Dual J-K negative edge-triggered flip-flop
74ALS112A
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn or RD to Qn or Qn
Waveform 1
Waveform 1
Waveform 2, 3
35
2.0
4.0
1.5
3.5
10.0
10.5
8.0
9.5
MAX
MHz
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
T
amb
= 0°C to +70°C
V
CC
= +5.0V
±
10%
C
L
= 50pF, R
L
= 500Ω
MIN
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
REC
Setup time, High or Low
Jn, Kn to CPn
Hold time, High or Low
Jn, Kn to CPn
CPn Pulse width
high or Low
SDn or RDn Pulse width
Low
Recovery time,
SDn or RDn to CPn
Waveform 1
Waveform 1
Waveform 1
Waveform 2, 3
Waveform 2, 3
8.0
8.0
0.0
0.0
11.0
8.0
6.0
8.0
MAX
ns
ns
ns
ns
ns
UNIT
1996 Jun 27
5
FPGA/CPLD
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