IS25LE256E
IS25LE128E
256/128Mb
IS25WE256E
IS25WE128E
SERIAL FLASH MEMORY 166MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
DATA SHEET
IS25LE256E/128E
IS25WE256E/128E
256/128Mb
SERIAL FLASH MEMORY 166MHZ MULTI I/O SPI &
QUAD I/O QPI DTR INTERFACE WITH ON CHIP ECC
FEATURES
Industry Standard Serial Interface
-
IS25LE256E: 256Mbit/32Mbyte
-
IS25LE128E: 128Mbit/16Mbyte
-
IS25WE256E: 256Mbit/32Mbyte
-
IS25WE128E: 128Mbit/16Mbyte
-
3 or 4 Byte Addressing Mode
-
Supports Standard SPI, Fast, Dual, Dual
I/O, Quad, Quad I/O, SPI DTR, Dual I/O
DTR, Quad I/O DTR, and QPI
-
Software & Hardware Reset
-
Supports Serial Flash Discoverable
Parameters (SFDP)
High Performance Serial Flash (SPI)
-
80MHz Normal Read
(3)
-
Up to166Mhz Fast Read
-
Up to 80MHz DTR (Dual Transfer Rate)
-
Equivalent Throughput of 664 Mb/s
-
Selectable Dummy Cycles
-
Configurable Drive Strength
-
Supports SPI Modes 0 and 3
-
More than 100,000 Erase/Program Cycles
-
More than 100-year Data Retention
-
1-bit ERROR Detection and Correction
per 64-bit boundary (with ECC)
Flexible & Efficient Memory Architecture
-
Chip Erase with Uniform Sector/Block
Erase (4/32/64KB or 4/32/256 KB)
(2)
-
Program 1 to 256 or 512 Byte per Page
(2)
-
Program/Erase Suspend & Resume
Efficient Read and Program modes
-
Low Instruction Overhead Operations
-
Continuous Read 8/16/32/64 Byte
Burst Wrap
-
Selectable Burst Length
-
QPI for Reduced Instruction Overhead
-
AutoBoot Operation
-
Data Learning Pattern for training in DTR
operation
Low Power with Wide Temp. Ranges
-
Single Voltage Supply
IS25LE: 2.30V to 3.60V
IS25WE: 1.70V to 1.95V
-
8 mA Active Read Current
-
10 µA Standby Current
-
1 µA Deep Power Down
-
Temp Grades:
Extended: -40°C to +105°C
Auto Grade (A3): -40°C to +125°C
Advanced Security Protection
-
Software and Hardware Write Protection
-
Advanced Sector/Block Protection
-
Top/Bottom Block Protection
-
Power Supply Lock Protection
-
4x256 Byte Dedicated Security Area
with OTP User-lockable Bits
-
128 bit Unique ID for Each Device
(Call Factory)
Industry Standard Pin-out & Packages
(1)
-
M =16-pin SOIC 300mil
-
L = 8-contact WSON 8x6mm
-
G = 24-ball TFBGA 6x8mm (4x6 ball array)
-
H = 24-ball TFBGA 6x8mm (5x5 ball array)
-
KGD
Notes:
1. Call Factory for other package options available.
2. For optional
512 Byte Page size with 256 KB
Block size, see the Ordering Information.
3. 80MHz for 3.0V device and 50MHz for 1.8V device.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A4
03/16/2020
2
IS25LE256E/128E
IS25WE256E/128E
GENERAL DESCRIPTION
The IS25LE256E/128E and IS25WE256E/128E Serial Flash memory offers a versatile storage solution with high
flexibility and performance in a simplified pin count package. ISSI’s “Industry Standard Serial Interface” Flash is
for systems that require limited space, a low pin count, and low power consumption. The device is accessed
through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK),
and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O (see pin descriptions).
The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies
of up to 166MHz allow for equivalent clock rates of up to 664MHz (166MHz x 4) which equates to 83Mbytes/s of
data throughput. The IS25xE series of Flash adds support for DTR (Double Transfer Rate) commands that transfer
addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash
memories allowing for efficient memory access to support XIP (execute in place) operation.
Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory.
QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be
erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64K/256Kbyte blocks, and/or the entire chip. The uniform
sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad
variety of applications requiring solid data retention.
Automatic ECC Protection (1-bit Error Correction) applies per every 64-bit to maximize reliability.
When ECC is ON, the device allows only single programming operation to each 8-byte ECC boundary between
erase operations.
Supply Voltage Range & Temperature Range vs. Maximum Speed
Voltage & Temp.
IS25LE(3.0V typ.)
IS25WE (1.8V typ.)
2.30~3.6V, 125
°C
2.70~3.6V, 125
°C
1.70~1.95V, 125
°C
1.70~1.95V, 105
°C
Maximum Speed
133MHz
166MHz
133MHz
166MHz
(1)
Note:
1. Values are guaranteed by characterization and not 100% tested in production.
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A4
03/16/2020
3
IS25LE256E/128E
IS25WE256E/128E
TABLE OF CONTENTS
FEATURES ........................................................................................................................................................... 2
GENERAL DESCRIPTION ................................................................................................................................... 3
TABLE OF CONTENTS ........................................................................................................................................ 4
1.
2.
3.
4.
5.
PIN CONFIGURATION .................................................................................................................................. 8
PIN DESCRIPTIONS ..................................................................................................................................... 9
BLOCK DIAGRAM ....................................................................................................................................... 11
SPI MODES DESCRIPTION ....................................................................................................................... 12
SYSTEM CONFIGURATION ....................................................................................................................... 14
5.1 BLOCK/SECTOR ADDRESSES ........................................................................................................... 14
5.2 Serial Flash Discoverable Parameters .................................................................................................. 16
6.
REGISTERS ................................................................................................................................................ 22
6.1 STATUS REGISTER ............................................................................................................................. 22
6.2 FUNCTION REGISTER ......................................................................................................................... 28
6.3 READ REGISTER AND EXTENDED REGISTER ................................................................................. 30
6.3.1 READ REGISTER ......................................................................................................................... 30
6.3.2 EXTENDED READ REGISTER ..................................................................................................... 33
6.4 AUTOBOOT REGISTER ....................................................................................................................... 35
6.5 BANK ADDRESS REGISTER ............................................................................................................... 36
6.6 ADVANCED SECTOR/BLOCK PROTECTION (ASP) RELATED REGISTER ..................................... 37
6.6.1 ADVANCED SECTOR/BLOCK PROTECTION REGISTER (ASPR) ............................................ 37
6.6.2 PASSWORD REGISTER .............................................................................................................. 38
6.6.3 PPB LOCK REGISTER ................................................................................................................. 38
6.6.4 PPB REGISTER ............................................................................................................................ 39
6.6.5 DYB REGISTER ............................................................................................................................ 39
6.6.6 DATA LEARNING PATTERN REGISTER .................................................................................... 40
6.7 ECC REGISTER .................................................................................................................................... 41
7.
PROTECTION MODE.................................................................................................................................. 42
7.1 HARDWARE WRITE PROTECTION..................................................................................................... 42
7.2 SOFTWARE WRITE PROTECTION ..................................................................................................... 42
7.2.1 BLOCK PROTECTION BITS ......................................................................................................... 42
7.2.2 ADVANCED SECTOR/BLOCK PROTECTION (ASP) .................................................................. 43
8.
DEVICE OPERATION ................................................................................................................................. 52
8.1 COMMAND OVERVIEW ....................................................................................................................... 52
8.2 COMMAND SET SUMMARY ................................................................................................................ 53
8.3 NORMAL READ OPERATION (NORD, 03h or 4NORD, 13h) .............................................................. 62
8.4 FAST READ OPERATION (FRD, 0Bh or 4FRD, 0Ch) .......................................................................... 65
8.5 HOLD OPERATION ............................................................................................................................... 69
8.6 FAST READ DUAL I/O OPERATION (FRDIO, BBh or 4FRDIO, BCh) ................................................. 70
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A4
03/16/2020
4
IS25LE256E/128E
IS25WE256E/128E
8.7 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh or 4FRDO, 3Ch).......................................... 74
8.8 FAST READ QUAD OUTPUT OPERATION (FRQO, 6Bh or 4FRQO 6Ch) ......................................... 77
8.9 FAST READ QUAD I/O OPERATION (FRQIO, EBh or 4FRQIO, ECh) ................................................ 80
8.10 PAGE PROGRAM OPERATION (PP, 02h or 4PP, 12h)..................................................................... 87
8.11 QUAD INPUT PAGE PROGRAM OPERATION (PPQ, 32h/38h or 4PPQ, 34h/3Eh) ......................... 90
8.12 ERASE OPERATION .......................................................................................................................... 91
8.13 SECTOR ERASE OPERATION (SER, D7h/20h or 4SER, 21h) ......................................................... 92
8.14 BLOCK ERASE OPERATION (BER32K:52h or 4BER32K:5Ch, BER64K/256K:D8h or
4BER64K/256K:DCh) .................................................................................................................................. 94
8.15 CHIP ERASE OPERATION (CER, C7h/60h) ...................................................................................... 97
8.16 WRITE ENABLE OPERATION (WREN, 06h) ..................................................................................... 98
8.17 WRITE DISABLE OPERATION (WRDI, 04h) ...................................................................................... 99
8.18 READ STATUS REGISTER OPERATION (RDSR, 05h) .................................................................. 100
8.19 WRITE STATUS REGISTER OPERATION (WRSR, 01h) ................................................................ 101
8.20 READ FUNCTION REGISTER OPERATION (RDFR, 48h) .............................................................. 102
8.21 WRITE FUNCTION REGISTER OPERATION (WRFR, 42h)............................................................ 103
8.22 ENTER QUAD PERIPHERAL INTERFACE (QPI) MODE OPERATION (QPIEN,35h; QPIDI,F5h) . 104
8.23 PROGRAM/ERASE SUSPEND & RESUME ..................................................................................... 105
8.24 ENTER DEEP POWER DOWN (DP, B9h) ........................................................................................ 108
8.25 RELEASE DEEP POWER DOWN (RDPD, ABh) .............................................................................. 109
8.26 SET READ PARAMETERS OPERATION (SRPNV: 65h, SRPV: C0h/63h) ..................................... 110
8.27 SET EXTENDED READ PARAMETERS OPERATION (SERPNV: 85h, SERPV: 83h) ................... 112
8.28 READ READ PARAMETERS OPERATION (RDRP, 61h) ................................................................ 113
8.29 READ EXTENDED READ PARAMETERS OPERATION (RDERP, 81h) ......................................... 114
8.30 CLEAR EXTENDED READ REGISTER OPERATION (CLERP, 82h) .............................................. 115
8.31 READ PRODUCT IDENTIFICATION (RDID, ABh) ........................................................................... 116
8.32 READ PRODUCT IDENTIFICATION BY JEDEC ID OPERATION (RDJDID, 9Fh; RDJDIDQ, AFh)
................................................................................................................................................................... 118
8.33 READ DEVICE MANUFACTURER AND DEVICE ID OPERATION (RDMDID, 90h) ....................... 119
8.34 READ UNIQUE ID NUMBER (RDUID, 4Bh) ..................................................................................... 120
8.35 READ SFDP OPERATION (RDSFDP, 5Ah) ..................................................................................... 121
8.36 NO OPERATION (NOP, 00h) ............................................................................................................ 121
8.37 SOFTWARE RESET (RESET-ENABLE (RSTEN, 66h) AND RESET (RST, 99h)) AND HARDWARE
RESET ....................................................................................................................................................... 122
8.38 SECURITY INFORMATION ROW ..................................................................................................... 123
8.39 INFORMATION ROW ERASE OPERATION (IRER, 64h) ................................................................ 124
8.40 INFORMATION ROW PROGRAM OPERATION (IRP, 62h) ............................................................ 125
8.41 INFORMATION ROW READ OPERATION (IRRD, 68h) .................................................................. 126
8.42 FAST READ DTR MODE OPERATION (FRDTR, 0Dh or 4FRDTR, 0Eh) ........................................ 127
8.43 FAST READ DUAL IO DTR MODE OPERATION (FRDDTR, BDh or 4FRDDTR, BEh) .................. 132
Integrated Silicon Solution, Inc.- www.issi.com
Rev.A4
03/16/2020
5
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