defining a degree of excellence
10 TAP LEADING EDGE CONTROL
LOW VOLTAGE DELAY MODULES
.60 + .01
13
.375
.350
12
3
Vcc 14
In 1
Gnd 7
Cat 31-R1
.60 + .01
.325
bel
(DC)
(P/N)
.285 Max
11 10 9
4
5
6
8
bel
*
(DC)
(P/N)
.285 Max
.10 Typ
.80 Max
.22 Max
.018
Coplanarity + .002
.10 Typ
.80 Max
.015
.004
4
o
.012
.008
.012
.008
.23 Max
100
o
90
o
.20 Max
.015 Min
.045
.030
.12 Min
.018
Part Numbers
SMD
S477-0025-10
S477-0030-10
S477-0040-10
S477-0050-10
S477-0060-10
S477-0070-10
S477-0080-10
S477-0090-10
S477-0100-10
S477-0125-10
S477-0150-10
S477-0200-10
S477-0250-10
Thru-Hole
Total
Delay
Delay
per Tap
2.5 ns
3 ns
4 ns
5 ns
6 ns
7 ns
8 ns
9 ns
10 ns
12.5 ns
15 ns
20 ns
25 ns
Rise
Time
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
3 ns
Ein
Trin
PW
PP
Iccl
Vcc
Test Conditions @ 25
o
C
Pulse Voltage
Rise Time
Pulse Width
Pulse Period
Supply Current
Supply Voltage
3.0 Volts
3.0 ns (10%-90%)
1.2 x Total Delay
4 x Pulse Width
30 ma Typical
3.3 Volts
A477-0025-10 * 22.5 ns
A477-0030-10
* 27 ns
A477-0040-10
* 36 ns
A477-0050-10
50 ns
A477-0060-10
60 ns
A477-0070-10
70 ns
A477-0080-10
A477-0090-10
A477-0100-10
A477-0125-10
A477-0150-10
A477-0200-10
A477-0250-10
80 ns
90 ns
100 ns
125 ns
150 ns
200 ns
250 ns
Electrical Characteristics
Vcc
Vih
Vil
Iik
Ioh
Iol
Voh
Vol
Vik
Iih
Iil
Icch
Iccl
Ta
PW
d
Tc
Supply Voltage
Logic 1 Input Voltage
Logic 0 Input Voltage
Input Clamp Current
Logic 1 Output Current
Logic 0 Output Current
Logic 1 Output Voltage
Logic 0 Output voltage
Input Clamp Voltage
Logic 1 Input Current
Logic 0 Input Current
Logic 1 Supply Current
Logic 0 Supply Current
Operating Free Air Temperature
Min. Input Pulse Width of Total Delay
Maximum Duty Cycle
Min.
3.0
2.4
Max.
3.6
0.8
-20
20
-20
2.9
0.1
-0.5
2
-2
10
40
70
o
50
Units
V
V
V
ma
ma
ma
V
V
V
ua
ua
ma
ma
C
%
%
Tolerances
Input to Taps + 2 ns or 5 % , Whichever is Greater
Tap to Tap + 2 ns or 7%, Whichever is Greater
Delays measured @ 50% levels on Leading Edge only
with no loads on Taps
Rise and Fall Times measured from 10% to 90% levels
* Ref. Delay from P13, Delay P1-P13 = 5.5 ns typical
0
o
40
Drive Capabilities
Nh Logic 1 Fanout
Nl Logic 0 Fanout
-
-
10 LSTTL Loads Max.
10 LSTTL Loads Max.
Temp. Coeff. of Total Delay (TD) 100 + (25000/TD) PPM/
O
C
Notes
Transfer molded for better reliability
Compatible with TTL & CMOS circuits
Terminals: Electro-Tin plate phosphor bronze
Performance warranty is limited to specified parameters listed
SMD - Tape & Reel available:
32mm Wide x 16mm Pitch, 500 pieces per 13" reel
Recommended Temperature Profile
300
o
C
200
o
C
100
o
C
Temp.
Infra Red
225
o
C Max Temp.
> 185
o
C
for 90 Seconds Max
0
2
4
6
Ti m e i n M i n u t e s
8
Other Delays and Tolerances Available
Consult Sales
Specifications subject to change without notice.
Corporate Office
Bel Fuse Inc.
198 Van Vorst Street, Jersey City, NJ 07302-4496
Tel: 201-432-0463
Fax: 201-432-9542
E-Mail: BelFuse@belfuse.com
Internet: http://www.belfuse.com
Far East Office
Bel Fuse Ltd.
8F/8 Luk Hop Street
San Po Kong
Kowloon, Hong Kong
Tel: 852-2328-5515
Fax: 852-2352-3706
European Office
Bel Fuse Europe Ltd.
Preston Technology Management Centre
Marsh Lane, Preston PR1 8UD
Lancashire, U.K.
Tel: 44-1772-556601
Fax: 44-1772-888366
25
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