FLASH
AS8F128K32
128K x 32 FLASH
FLASH MEMORY ARRAY
AVAILABLE AS MILITARY
SPECIFICATIONS
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SMD 5962-94716
MIL-STD-883
Fast Access Times: 60, 70, 90, 120 and 150ns
Operation with single 5V (±10%)
Compatible with JEDEC EEPROM command set
Any Combination of Sectors can be Erased
Supports Full Chip Erase
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
Hardware Data Protection
Data\ Polling and Toggle Bits
Low Power consumption
Individual Byte Read/ Write Control
Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
GND
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Vcc
A11
A12
A13
A14
A15
A16
CS1\
OE
CS2\
NC
WE2\
WE3\
WE4\
NC
NC
NC
PIN ASSIGNMENT
(Top View)
68 Lead CQFP (Q & Q1)
NC
A0
A1
A2
A3
A4
A5
CS3\
GND
CS4\
WE1\
A6
A7
A8
A9
A10
Vcc
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
GND
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
FEATURES
OPTIONS
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Timing
60ns
70ns
90ns
120ns
150ns
Package
Ceramic Quad Flat pack
Ceramic Quad Flat pack
MARKINGS
-60
-70
-90
-120
-150
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Q
Q1
No. 703
GENERAL DESCRIPTION
The AS8F128K32 is a 4 Megabit CMOS FLASH Memory
Module organized as 128K x 32 bits. The AS8F128K32 achieves
high speed access (60 to 150 ns), low power consumption and high
reliability by employing advanced CMOS memory technology.
The device is designed to be programmed in-system with the stan-
dard system 5.0V V
CC
supply. A 12.0V V
PP
is not required for program
or erase operation. The device can also be programmed or erased in
standard EPROM programmers. To eliminate bus
contention
the device has seperate chip enbaled (CEx\), write enable (WEx\) and
output enable (OE) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated voltages
are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC
single-power-supply Flash standard. Commands are written to the com-
mand register using standard microprocessor write timings. Register
contents serve as input to an internal state machine that controls the
AS8F128K32
Rev. 2.8 01/10
erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations.
Reading data out of the device is similar to reading from other Flash
or EPROM devices.
Device programming occurs by executing the program command
sequence. This invokes the Embedded Program algorithm—an inter-
nal algorithm that automatically times the program pulse widths and
verifies proper cell margin.
Device erasure occurs by executing the erase command sequence.
This invokes the Embedded Erase algorithm—an internal algorithm
that automatically preprograms the array (if it is not already
pro-
grammed) before executing the erase operation. During erase, the
device automatically times the erase pulse widths and verifies proper
cell margin.
The host system can detect whether a program or erase operation
is complete by reading the I/O7 (Data\ Polling) and I/O6 (toggle) status
bits. After a program or erase cycle has been completed, the device is
ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased
and reprogrammed without affecting the data contents of other sectors.
The device is erased when shipped from the factory.
The hardware data protection measures include a low V
CC
detector automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both
program and erase operations in any combination of the sectors of
memory, and is implemented using standard EPROM programmers.
The system can place the device into the standby mode. Power
consumption is greatly reduced in this mode.
The device electrically erases all bits within a sector simultane-
ously via Fowler-Nordheim tunneling. The bytes are programmed
one byte at a time using the EPROM programming mechanism of
hot electron injection.
For more products and information
please visit our web site at
www.micross.com
Micross Components reserves the right to change products or specifications without notice.
1
FLASH
AS8F128K32
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
PIN
A0 - A16
I/O0 - I/O31
CEx\
OE\
WEx\
V
CC
DESCRIPTION
Addresses
Input/Output
Chip Enable
Output Enable
Write Enable
LOGIC SYMBOL
5.0V Power Supply
GND
Device Ground
x
NC
2, 3 or 4
No Connect
= 1,
AS8F128K32
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifications without notice.
2
FLASH
AS8F128K32
DEVICE BUS OPERATIONS
NOTE: All device/algorithm descriptions contained in this
data sheet reference each individual die.
This section describes the requirements and use of the
device bus operations, which are initiated through the inter-
nal command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of
the device. The appropriate device bus operations table lists
the inputs and control levels required, and the resulting output.
The following subsections describe each of these operations in
further detail.
the command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifications and
to the Read Operations Timings diagram for the timing wave-
forms. I
CC1
in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing sectors of
memory), the system must drive WEx\ and CEx\ to V
IL
, and
OE\ to V
IH
.
An erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the address
space that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. See the
“Command Definitions” section for details on erasing a sector
or the entire chip.
After the system writes the autoselect command se-
quence,
the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on I/O31–I/O0. Standard read cycle
timings apply in this mode. Refer to the “Autoselect Mode”
and “Autoselect Command Sequence” sections for more
information. I
CC2
in the DC Characteristics table represents
the active current specification for the write mode. The “AC
Characteristics” section contains timing specification tables
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CEx\ and OE\ pins to V
IL
. CEx\ is the power control and
selects the device. OE\ is the output control and gates array
data to the output pins. WEx\ should remain at V
IH
.
The internal state machine is set for reading array data
upon device power-up. This ensures that no spurious altera-
tion of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access until
TABLE 1: Device Bus Operations
1
OPERATION
Read
Write
Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
CEx\
L
L
V
CC
± 0.5V
L
X
X
OE\
L
H
X
H
X
X
WEx\
H
L
X
H
X
X
ADRESSES
(A16:A0)
A
IN
A
IN
X
X
X
A
IN
I/O0 - I/O31
D
OUT
D
IN
High-Z
High-Z
High-Z
D
IN
LEGEND:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0 ± 0.5 V, X = Don’t Care, A
IN
= Addresses In, D
IN
= Data In, D
OUT
= Data Out
NOTES:
1. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section.
AS8F128K32
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifications without notice.
3
FLASH
AS8F128K32
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits on I/
O31–I/O0. Standard read cycle timings and I
CC
read specifica-
tions apply. Refer to “Write Operation Status” for more informa-
tion, and to each AC Characteristics section in the appropriate
data sheet for timing diagrams.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O31–I/O0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
requires V
ID
(11.5 V to 12.5 V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in Autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don’t care. When all necessary
bits have been set as required, the programming equipment may
then read the corresponding identifier code on I/O31–
I/
O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register,
as shown in the Command Definitions table. This method does
not require V
ID
. See “Command Definitions” for details on
using the autoselect mode.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE\ input.
The device enters the CMOS standby mode when the CEx\
pin is held at V
CC
± 0.5 V. (Note that this is a more restricted
voltage range than V
IH
.) The device enters the TTL standby
mode when CEx\ is held at V
IH
. The device requires the stan-
dard access time (t
CE
) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is completed.
I
CC3
in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE\ input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
TABLE 2: Sector Addresses Table (Each Byte)
SECTOR
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
A16
0
0
0
0
1
1
1
1
A15
0
0
1
1
0
0
1
1
A14
0
1
0
1
0
1
0
1
ADDRESS RANGE
00000h - 03FFFh
04000h - 07FFFh
08000h - 0BFFFh
0C000h - 0FFFFh
10000h - 13FFFh
14000h - 17FFFh
18000h - 1BFFFh
1C000h - 1FFFFh
AS8F128K32
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifications without notice.
4
FLASH
AS8F128K32
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented us-
ing programming equipment. The procedure requires a high
voltage (V
ID
) on address pin A9 and the control pins.
The device is shipped with all sectors unprotected. It is
possible to determine whether a sector is protected or
un-
protected. See “Autoselect Mode” for details.
Low VCC Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept
any write cycles. This protects data during V
CC
power-up and
power-down. The command register and all internal program/
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to prevent
unintentional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE\, CEx\ or
WEx\ do not initiate a write cycle.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
V
CC
power-up and power-down transitions, or from system
noise.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = V
IL
,
CEx\ = V
IH
or WEx\ = V
IH
. To initiate a write cycle, CEx\ and
WEx\ must be a logical zero while OE\ is a logical one.
Power-Up Write Inhibit
If WEx\ = CEx\ = V
IL
and OE\ = V
IH
during power up, the
device does not accept commands on the rising edge of WEx\.
The internal state machine is automatical ly reset to reading
array data on power-up.
TABLE 3: Autoselect Codes (High Voltage Method)
DESCRIPTION
CEx\
L
L
OE\
L
L
WEx\
H
H
A16
to
A14
X
X
A13
to
A10
X
X
A9
V
ID
V
ID
A8 to
A6
A7
X
X
L
L
A5
to
A2
X
X
A1
L
L
A0
L
H
I/O0 to I/O7
I/O8 to I/O15
I/O16 to I/O23
I/O24 to I/O31
01h
20h
01h (protected)
L
Sector Protection Verification
LEGEND:
L = Logic Low = V
IL
, H = Logic High = V
IH
, SA = Sector Address, X = Don’t care.
Manufacturer ID: AMD
Device ID: AM29F010B
L
H
SA
X
V
ID
X
L
X
H
L
00h
(unprotected)
AS8F128K32
Rev. 2.8 01/10
Micross Components reserves the right to change products or specifications without notice.
5
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