INTEGRATED CIRCUITS
DATA SHEET
TZA3034T; TZA3034U
SDH/SONET STM1/OC3
postamplifiers
Objective specification
File under Integrated Circuits, IC19
1998 Jul 07
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 postamplifiers
FEATURES
•
Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count
•
Wideband operation from 1.0 kHz to 150 MHz typical
•
Applicable in 155 Mbits/s SDH/SONET receivers
•
Single supply voltage from 3.0 to 5.5 V
•
PECL (Positive Emitter Coupled Logic) compatible data
outputs
•
Programmable input signal level-detection which can be
adjusted using a single external resistor
•
On-chip DC offset compensation without external
capacitor
•
Fully differential for excellent PSRR.
APPLICATIONS
TZA3034T; TZA3034U
•
Digital fibre optic receiver in short, medium and long
haul optical telecommunications transmission systems
or in high speed data networks
•
Wideband RF gain block.
GENERAL DESCRIPTION
The TZA3034 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3033. It is pin compatible with the NE/SA5224
and NE/SA5225 but with extended power supply range,
and needs less external components. Capable of
operating at 155 Mbits/s, the chip has input signal level
detection with a user-programmable threshold. The data
and level-detection status outputs are differential outputs
for optimum noise margin and ease of use.
ORDERING INFORMATION
TYPE
NUMBER
TZA3034T
TZA3034U
PACKAGE
NAME
SO16
naked die
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm
die in waffle pack carriers; die dimensions 1.58
×
1.58 mm
VERSION
SOT109-1
−
BLOCK DIAGRAM
handbook, full pagewidth
TEST
2
(2, 10, 15, 21, 26)
DC-OFFSET
COMPENSATION
DIN
DINQ
4 (7)
5 (8)
A1
A2
A3
TZA3034
(24) 13
(23) 12
(16) 8
(18) 10
DOUT
DOUTQ
JAM
ST
STQ
25 kΩ
RECTIFIER
RSET
Vref
16 (30)
15 (29)
1 kΩ
A4
BAND GAP
REFERENCE
(17) 9
(3, 4, 6, 9)
3
AGND
(1, 14)
1
(11, 12)
6
VCCA
(13)
7
CF
(19, 20, 22, 25)
11
(27, 28)
14
MGR281
SUB
DGND
VCCD
The numbers in brackets refer to the pad numbers of the naked die version.
Fig.1 Block diagram.
1998 Jul 07
2
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 postamplifiers
PINNING
SYMBOL
SUB
TEST
AGND
DIN
DINQ
V
CCA
CF
JAM
PIN
1
2
3
4
5
6
7
8
TYPE
substrate
test pin
ground
analog input
analog input
supply
analog input
PECL input
TZA3034T; TZA3034U
DESCRIPTION
substrate pin; must be at the same potential as AGND (pin 3)
for test purpose only; to be left open in the application
analog ground; must be at the same potential as DGND (pin 11)
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DINQ (pin 5)
differential input; DC bias level is set internally at approximately 2.55 V;
complimentary to DIN (pin 4)
analog supply voltage; must be at the same potential as V
CCD
(pin 14)
filter capacitor for input signal level detector; capacitor should be connected
between this pin and V
CCA
(pin 6)
PECL-compatible input; controls the output buffers DOUT and DOUTQ
(pins 13 and 12). When a LOW signal is applied, the outputs will follow the input
signal3 When a HIGH signal is applied, the DOUT and DOUTQ pins will latch into
LOW and HIGH states, respectively. When left unconnected, this pin is actively
pulled LOW (JAM OFF).
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is HIGH;
complimentary to ST (pin 10)
PECL-compatible status output of the input signal level detector; when the input
signal is below the user-programmed threshold level, this output is LOW;
complimentary to STQ (pin 9)
digital ground; must be at the same potential as AGND (pin 3)
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a HIGH condition; complimentary to DOUT (pin 13)
PECL-compatible differential output; when JAM is HIGH, this pin will be forced
into a LOW condition; complimentary to DOUTQ (pin 12)
digital supply voltage; must be at the same potential as V
CCA
(pin 6)
input signal level detector programming; nominal DC voltage is V
CCA
−
1.5 V;
threshold level is set by connecting an external resistor between RSET and V
CCA
or by forcing a current into RSET; default value for this resistor is 180 kΩ which
corresponds with approximately 4 mV (p-p) differential input signal
STQ
9
PECL output
ST
10
PECL output
DGND
DOUTQ
DOUT
V
CCD
V
ref
RSET
11
12
13
14
15
16
ground
PECL output
PECL output
supply
analog input
analog output band gap reference voltage; typical value is 1.2 V; internal series resistor of 1 kΩ
1998 Jul 07
3
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 postamplifiers
TZA3034T; TZA3034U
PAD CONFIGURATION
Pad centre locations
handbook, halfpage
SUB 1
TEST 2
AGND 3
DIN 4
16 RSET
15 Vref
14 VCCD
13 DOUT
COORDINATES
(1)
SYMBOL
SUB
TEST
AGND
AGND
n.c.
AGND
DIN
DINQ
AGND
TEST
PAD
x
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
−235.7
−392.8
−532.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−532.8
−392.8
−235.7
−78.6
+61.4
+218.5
+375.6
+532.7
+647.8
+647.8
+647.8
+647.8
647.8
647.8
647.8
647.8
532.7
392.7
235.6
78.5
−78.6
y
+647.8
+647.8
+647.8
+507.1
+350.0
+210.0
+70.0
−70.0
−210.0
−350.0
−507.1
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−647.8
−507.1
−350.0
−210.0
−70.0
70.0
210.0
350.0
507.1
647.8
647.8
647.8
647.8
+647.8
TZA3034T
DINQ 5
VCCA 6
CF 7
JAM 8
MGR282
12 DOUTQ
11 DGND
10 ST
9
STQ
Fig.2 Pin configuration.
V
CCA
V
CCA
CF
SUB
TEST
JAM
STQ
ST
DGND
DGND
TEST
DGND
DOUTQ
DOUT
DGND
TEST
V
CCD
V
CCD
V
ref
RSET
n.c.
n.c.
Note
1. Coordinates represent the position of the centre of the
pad, in
µm,
with respect to the centre of the die.
1998 Jul 07
4
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 postamplifiers
Bonding pad locations
AGND
VCCD
28
27
26
25
x
0
0
y
24
23
22
21
20
12
VCCA
13
CF
14
SUB
15
TEST
16
JAM
17
STQ
18
ST
19
DGND
TZA3034T; TZA3034U
SUB
3
AGND
n.c.
AGND
1.58
(1)
mm
DIN
DINQ
AGND
TEST
VCCA
4
5
6
7
8
9
10
11
2
1
32
31
30
29
Vref
handbook, full pagewidth
RSET
TEST
n.c.
n.c.
VCCD
TEST
DGND
DOUT
DOUTQ
DGND
TEST
DGND
TZA3034U
1.58 mm
(1)
MGR283
(1) Typical value.
Pad size: 90
×
90
µm.
Fig.3 Bonding pad locations: TZA3034U.
FUNCTIONAL DESCRIPTION
The TZA3034 accepts up to 155 Mbits/s SD/SONET data
streams, with amplitudes from 2 mV (p-p) up to 1 V (p-p)
single-ended. The input signal will be amplified and limited
to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3034, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ. This flag can also be used to prevent
the PECL outputs DOUT and DOUTQ from reacting to
noise in the absence of a valid input signal, by connecting
the output STQ to the input JAM. This insures that data will
only be transmitted when the input signal-to-noise ratio is
sufficient for low bit error rate system operation.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The input pins DIN and DINQ are DC biased at
approximately 2.55 V by an internal reference generator
(see Fig.5). The TZA3034 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (2.0 V to V
CCA
+ 0.5 V). Also a DC offset voltage of
1998 Jul 07
5
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