INTEGRATED CIRCUITS
74F109
Positive J-K positive edge-triggered
flip-flops
Product specification
IC15 Data Handbook
1990 Oct 23
Philips
Semiconductors
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
FEATURE
•
Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F109 is a dual positive edge-triggered JK-type flip-flop
featuring individual J, K, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock (CP) input.
The J and K are edge-triggered inputs which control the state
changes of the flip-flops as described in the function table. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. The J and K inputs must
be stable just one setup time prior to the low-to-high transition of the
clock for predictable operation. The JK design allows operation as a
D flip-flop by tying J and K inputs together. Although the clock input
is level sensitive, the positive transition of the clock pulse between
the 0.8V and 2.0V levels should be equal to or less than the clock to
output delay time for reliable operation.
TYPE
74F109
TYPICAL f
max
125MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
12.3mA
PIN CONFIGURATION
RD0
J0
K0
CP0
SD0
Q0
Q0
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RD1
J1
K1
CP1
SD1
Q1
Q1
SF00135
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
16-pin plastic DIP
16-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F109N
N74F109D
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40°C to +85°C
I74F109N
I74F109D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
J0, J1
K0, K1
CP0, CP1
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
J inputs
K inputs
Clock inputs (active rising edge)
Set inputs (active Low)
Reset inputs (active Low)
Data outputs
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/3.0
1.0/3.0
50/33
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/0.6mA
20µA/1.8mA
20µA/1.8mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
2 14
3 13
IEC/IEEE SYMBOL
2
4
1J
C1
1K
R
S
10
7
6
4
5
1
12
11
15
CP0
SD0
RD0
CP1
SD1
RD1
J0
J1
K0 K1
3
1
5
14
Q0 Q0 Q1 Q1
12
13
15
6
7
10
9
11
2J
C2
2K
R
S
9
V
CC
= Pin 16
GND = Pin 8
SF00136
SF00137
October 23, 1990
2
853–0337 00783
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
LOGIC DIAGRAM
7, 9
6, 10
FUNCTION TABLE
INPUTS
OUTPUTS
J
X
X
X
X
h
h
l
l
K
X
X
X
X
l
h
l
h
Q
H
L
H
q
q
H
L
q
Q
L
H
H
q
q
L
H
q
OPERATING MODE
Asynchronous set
Asynchronous reset
Undetermined*
Hold
Toggle
Load ”1” (set)
Load ”0” (reset)
Hold ’no change”
SD
L
H
L
H
RD
H
L
L
H
H
H
H
H
CP
X
X
X
↑
↑
↑
↑
↑
Q
Q
3, 13
K
2, 14
4, 12
5, 11
1, 15
H
H
H
H
J
CP
SD
RD
V
CC
= Pin 16
GND = Pin 8
SF00138
NOTES:
H = High-voltage level
h = High-voltage level one setup time prior to low-to-high
clock transition
L = Low-voltage level
l = Low-voltage level one setup time prior to low-to-high
clock transition
q = Lower case indicate the state of the referenced output
prior to the low-to-high clock transition
X = Don’t care
↑
= Low-to-high clock transition
↑
= Not low-to-high clock transition
* = Both outputs will be high if both SD and RD go low
simultaneously
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Commercial range
Operating free-air temperature range
free air
Industrial range
Storage temperature range
–40 to +85
–65 to +150
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
UNIT
V
V
mA
V
mA
°C
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
V
IN
V
IL
I
IK
I
OH
I
OL
T
amb
Supply voltage
High-level input voltage
Low-level input voltage
Input clamp current
High-level output current
Low-level output current
Commercial range
Operating free-air temperature range
free air
Industrial range
3
0
–40
PARAMETER
MIN
4.5
2.0
0.8
–18
–1
20
+70
+85
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
°C
°C
UNIT
October 23, 1990
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS
1
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN
V
CC
= MIN, I
I
= I
IK
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
J, K, CPn
SDn, RDn
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
-60
LIMITS
MIN
TYP
2
MAX
UNIT
V
3.4
0.30
0.30
–0.73
0.50
0.50
–1.2
100
20
–0.6
–1.8
–150
V
V
V
V
µA
µA
mA
mA
mA
V
O
OH
High-level
High level output voltage
I
O
= MAX
OH
I
OL
= MAX
±
10%V
CC
±
5%V
CC
±
10%V
CC
±
5%V
CC
2.5
2.7
V
O
OL
V
IK
I
I
I
IH
I
IL
I
OS
Low-level
Low level output voltage
Input clamp voltage
Input current at maximum input voltage
High-level input current
Low-level
Low level input current
Short-circuit output current
3
I
CC
Supply current
4
(total)
V
CC
= MAX
12.3
17
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
4. Measure I
CC
with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF
R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, RD to Qn or Qn
Waveform 1
Waveform 1
Waveform 2, 3
90
3.8
4.4
3.2
3.5
TYP
125
5.3
6.2
5.2
7.0
7.0
8.0
7.0
9.0
MAX
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF
R
L
= 500Ω
MIN
90
3.8
4.4
3.2
3.5
8.0
9.2
8.0
10.5
MAX
V
CC
= +5.0V
±
10%
T
amb
= –40°C to +85°C
C
L
= 50pF
R
L
= 500Ω
MIN
90
3.8
4.4
2.8
3.5
9.0
9.2
9.0
10.5
MAX
MHz
ns
ns
UNIT
AC SETUP REQUIREMENTS
LIMITS
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF
R
L
= 500Ω
MIN
t
su
(H)
t
su
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
t
w
(L)
t
rec
Setup time, high or low
Dn to CPn
Hold time, high or low
Dn to CPn
CP pulse width,
high or low
SDn or RDn pulse width,
low
Recovery time
SDn or RDn to CP
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 3
3.0
3.0
1.0
1.0
4.0
5.0
4.0
2.0
TYP
MAX
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF
R
L
= 500Ω
MIN
3.0
3.0
1.0
1.0
4.0
5.0
4.0
2.0
MAX
V
CC
= +5.0V
±
10%
T
amb
= –40°C to +85°C
C
L
= 50pF
R
L
= 500Ω
MIN
3.0
3.0
1.0
1.0
4.0
5.0
4.0
2.0
MAX
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
UNIT
October 23, 1990
4
Philips Semiconductors
Product specification
Postive J-K positive edge-triggered flip-flops
74F109
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Jn, Kn
V
M
t
su
(L)
V
M
t
h
(L)
1/f
max
V
M
t
su
(H)
V
M
t
h
(H)
CPn
V
M
t
w
(H)
t
PLH
V
M
t
w
(L)
V
M
t
PHL
Qn
V
M
t
PHL
V
M
t
PLH
Qn
V
M
V
M
SF00139
Waveform 1. Propagation Delay for Data to Output, Data Setup
Time and Hold Times, and Clock Width,and Maximum
Clock Frequency
SDn V
M
t
w
(L)
V
M
RDn
t
PLH
Qn
V
M
t
PHL
Qn
V
M
t
w
(L)
V
M
t
PHL
V
M
V
M
t
PLH
V
M
SF00050
Waveform 2. Propagation Delay for Set and Reset to Output,
Set and Reset Pulse Width
SDn or RDn
V
M
t
rec
CPn
V
M
SF00051
Waveform 3. Recovery Timer for Set or Reset to Clock
October 23, 1990
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
