INTEGRATED CIRCUITS
DATA SHEET
74HC08; 74HCT08
Quad 2-input AND gate
Product specification
Supersedes data of 1990 Dec 01
2003 Jul 25
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
FEATURES
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns.
DESCRIPTION
The 74HC/HCT08 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT08 provide the 2-input
AND function.
TYPICAL
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. For 74HC08: the condition is V
I
= GND to V
CC
.
For 74HCT08: the condition is V
I
= GND to V
CC
−
1.5 V.
FUNCTION TABLE
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
nB
L
H
L
H
OUTPUT
nY
L
L
L
H
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
notes 1 and 2
CONDITIONS
74HC08
C
L
= 15 pF; V
CC
= 5 V
7
3.5
10
74HCT08
11
3.5
20
ns
pF
pF
UNIT
2003 Jul 25
2
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
74HC08N
74HCT08N
74HC08D
74HCT08D
74HC08DB
74HCT08DB
74HC08PW
74HCT08PW
74HC08BQ
74HCT08BQ
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYMBOL
1A
1B
1Y
2A
2B
2Y
GND
3Y
3A
3B
4Y
4A
4B
V
CC
data input
data input
data output
data input
data input
data output
ground (0 V)
data output
data input
data input
data output
data input
data input
supply voltage
DESCRIPTION
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
−40
to +125
°C
PINS
14
14
14
14
14
14
14
14
14
14
PACKAGE
DIP14
DIP14
SO14
SO14
SSOP14
SSOP14
TSSOP14
TSSOP14
DHVQFN14
DHVQFN14
MATERIAL
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
plastic
CODE
SOT27-1
SOT27-1
SOT108-1
SOT108-1
SOT337-1
SOT337-1
SOT402-1
SOT402-1
SOT762-1
SOT762-1
2003 Jul 25
3
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
handbook, halfpage
handbook, halfpage
1A
1
VCC
14
13
12
4B
4A
4Y
3B
3A
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
MNA220
14 VCC
13 4B
12 4A
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
Top view
GND
8
3Y
08
11 4Y
10 3B
9
3A
GND
(1)
11
10
9
8 3Y
MCE183
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration DIP14, SO14 and
(T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
handbook, halfpage
handbook, halfpage
1
2
&
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
&
6
2Y
6
5
3Y
8
9
10
&
8
4Y
11
12
MNA222
&
11
13
MNA223
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
2003 Jul 25
4
Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
A
handbook, halfpage
Y
B
MNB037
handbook, halfpage
A
Y
B
MNA221
Fig.5 HC logic diagram (one gate).
Fig.6 HCT logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS
74HC08
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
ambient
temperature
input rise and fall
times
CONDITIONS
MIN.
2.0
0
0
see DC and AC
−40
characteristics per device
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
−
−
−
TYP.
5.0
−
−
+25
−
6.0
−
MAX.
6.0
V
CC
V
CC
+125
1000
500
400
MIN.
4.5
0
0
−40
−
−
−
TYP.
5.0
−
−
+25
−
6.0
−
MAX.
5.5
V
CC
V
CC
+125
−
500
−
V
V
V
°C
ns
ns
ns
74HCT08
UNIT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
I
OK
I
O
I
CC
, I
GND
T
stg
P
tot
PARAMETER
supply voltage
input diode current
output diode current
output source or sink current
V
CC
or GND current
storage temperature
power dissipation
DIP14 package
other packages
Notes
1. For DIP14 packages: above 70
°C
derate linearly with 12 mW/K.
2. For SO14 packages: above 70
°C
derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60
°C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
derate linearly with 4.5 mW/K.
2003 Jul 25
5
T
amb
=
−40
to +125
°C;
note 1
T
amb
=
−40
to +125
°C;
note 2
−
−
750
500
mW
mW
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
CONDITIONS
−
−
−
−
−65
MIN.
−0.5
MAX.
+7.0
±20
±20
±25
±50
+150
V
mA
mA
mA
mA
°C
UNIT
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