ADVANCE
‡
256Mb: x16
MOBILE SDRAM
MOBILE SDRAM
FEATURES
• Temperature Compensated Self Refresh (TCSR)
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Deep Power Down
• Partial Array Self Refresh power-saving mode
• Industrial operating temperature (-40
o
C to +85
o
C)
MT48V16M16LFFG, MT48H16M16LFFG–
4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
PIN ASSIGNMENT (Top View)
54-Ball FBGA
1
A
B
C
D
E
F
G
H
J
V
SS
DQ14
DQ12
DQ10
DQ8
UDQM
NC/A12
A8
V
SS
2
DQ15
DQ13
DQ11
DQ9
NC
CK
A11
A7
A5
3
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
CKE
A9
A6
A4
4
5
6
7
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
CAS\
BA0
A0
A3
8
DQ0
DQ2
DQ4
DQ6
LDQM
RAS\
BA1
A1
A2
9
V
DD
DQ1
DQ3
DQ5
DQ7
WE\
CS\
A10
VDD
OPTIONS
• V
DD
/V
DD
Q
2.5V/1.8V
1.8V/1.8V
• Configurations
16 Meg x 16 (4 Meg x 16 x 4 banks)
• WRITE Recovery (
t
WR/
t
DPL)
t
WR = 2 CLK
• Plastic Packages – OCPL
1
54-ball FBGA (8mm x 14mm)
• Timing (Cycle Time)
8.0ns @ CL = 3 (125MHz)
10ns @ CL = 3 (100MHz)
MARKING
V
H
16M16
FG
1
-8
-10
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 16
4 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
NOTE:
1. See page 58 for FBGA Device Marking Table.
256Mb SDRAM PART NUMBERS
PART NUMBER
MT48V16M16LFFG
MT48H16M16LFFG
ARCHITECTURE
16 Meg x 16
16 Meg x 16
VDD
2.5V
1.8V
KEY TIMING PARAMETERS
SPEED
GRADE
-8
-10
-8
-10
-8
-10
CLOCK
FREQUENCY
125 MHz
100 MHz
100 MHz
83 MHz
50 MHz
40 MHz
ACCESS TIME
CL=1* CL=2* CL=3*
–
–
–
–
19ns
22ns
–
–
8ns
8ns
–
–
7ns
7ns
–
–
–
–
SETUP HOLD
TIME TIME
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
2.5ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
1.0ns
*CL = CAS (READ) latency
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
‡
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
ADVANCE
256Mb: x16
MOBILE SDRAM
256Mb SDRAM PART NUMBERS
PART NUMBER
MT48V16M16LFFG-10
MT48V16M16LFFG-8
MT48H16M16LFFG-10
MT48H16M16LFFG-8
V
DD
/V
DD
Q
2.5V / 1.8V
2.5V / 1.8V
1.8V / 1.8V
1.8V / 1.8V
ARCHITECTURE
16 Meg x 16
16 Meg x 16
16 Meg x 16
16 Meg x 16
PACKAGE
54-BALL FBGA
54-BALL FBGA
54-BALL FBGA
54-BALL FBGA
GENERAL DESCRIPTION
The 256Mb SDRAM is a high-speed CMOS,
dynamic random-access memory containing
268,435,456 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 67,108,864-bit banks is orga-
nized as 8,192 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed (BA0, BA1
select the bank; A0–A12 select the row). The address
bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location
for the burst access.
The SDRAM provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.
The 256Mb SDRAM uses an internal pipelined ar-
chitecture to achieve high-speed operation. This ar-
chitecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless, high-
speed, random-access operation.
The 256Mb SDRAM is designed to operate in 2.5V
and 1.8V memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM oper-
ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks to hide precharge time and
the capability to randomly change column addresses
on each clock cycle during a burst access.
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16
MOBILE SDRAM
TABLE OF CONTENTS
Functional
Block Diagram – 16 Meg x 16 ..................
54-Ball FBGA Pin Description ....................................
Functional Description
...............................................
Initialization ...........................................................
Register Definition ................................................
Mode Register ...................................................
Burst Length ................................................
Burst Type ...................................................
CAS Latency ................................................
Operating Mode ..........................................
Write Burst Mode ........................................
Extended Mode Register ...........................
Temperature Compensated Self Refresh
Partial Array Self Refresh ...........................
Deep Power Down ......................................
Driver Strength ...........................................
Commands
...................................................................
Truth Table 1 (Commands and DQM Operation)
..............
Command Inhibit ..................................................
No Operation (NOP) ..............................................
Load mode register ................................................
Active .......................................................................
Read .......................................................................
Write .......................................................................
Precharge ................................................................
Auto Precharge .......................................................
Auto Refresh ...........................................................
Self Refresh .............................................................
Operation
.....................................................................
Bank/Row Activation .............................................
Reads .......................................................................
Writes .......................................................................
Precharge ................................................................
Power-Down ...........................................................
Deep Power-Down ................................................
Clock Suspend ........................................................
Burst Read/Single Write .......................................
Concurrent Auto Precharge .................................
4
5
6
6
6
6
6
7
8
8
8
9
9
10
10
10
11
11
12
12
12
12
12
12
12
12
12
13
14
14
15
21
23
23
24
24
24
25
27
28
30
Absolute Maximum Ratings ....................................... 32
DC Electrical Characteristics
and Operating Conditions .....................................
32
Capacitance .................................................................. 33
AC Electrical Characteristics
(Timing Table) ......... 33
I
DD
Specifications and Conditions ............................. 35
Timing Waveforms
Initialize and Load mode register ........................
Power-Down Mode ................................................
Clock Suspend Mode ............................................
Auto Refresh Mode ................................................
Self Refresh Mode ..................................................
Reads
Read – Without Auto Precharge .....................
Read – With Auto Precharge ...........................
Single Read – Without Auto Precharge .........
Single Read – With Auto Precharge ...............
Alternating Bank Read Accesses ....................
Read – Full-Page Burst ....................................
Read – DQM Operation ...................................
Writes
Write – Without Auto Precharge .....................
Write – With Auto Precharge ...........................
Single Write - Without Auto Precharge .........
Single Write - Without Auto Precharge .........
Alternating Bank Write Accesses ...................
Write – Full-Page Burst ....................................
Write – DQM Operation ...................................
Package Dimensions
54-pin FBGA ............................................................
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Truth Table 2 (CKE)
......................................................
Truth Table 3 (Current State, Same Bank)
......................
Truth Table 4 (Current State, Different Bank)
.................
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16
MOBILE SDRAM
FUNCTIONAL BLOCK DIAGRAM
16 Meg x 16 SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
COMMAND
DECODE
MODE REGISTER
REFRESH 13
COUNTER
12
13
ROW-
ADDRESS
MUX
13
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
8192
BANK0
MEMORY
ARRAY
(8,192 x 512 x 16)
2
2
DQML,
DQMH
SENSE AMPLIFIERS
16
8192
DATA
OUTPUT
REGISTER
2
A0-A12,
BA0, BA1
ADDRESS
REGISTER
BANK
CONTROL
LOGIC
15
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
16
512
(x16)
16
DQ0-
DQ15
2
DATA
INPUT
REGISTER
COLUMN
DECODER
COLUMN-
ADDRESS
COUNTER/
LATCH
9
9
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
ADVANCE
256Mb: x16
MOBILE SDRAM
BALL DESCRIPTIONS
54-BALL FBGA
F2
SYMBOL
CLK
TYPE
Input
DESCRIPTION
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CLK. CLK also increments the internal burst counter
and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or
CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external bank selection on systems with multiple banks. CS# is
considered part of the command code.
Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z state
(two-clock latency) when during a READ cycle. LDQM corresponds to DQ0–DQ7,
UDQM corresponds to DQ8–DQ15. LDQM and UDQM are considered same
state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied. These pins also provide the
op-code during a LOAD MODE REGISTER command
Address Inputs: A0–A12 are sampled during the ACTIVE command (row-
address A0–A12) and READ/WRITE command (column-address A0–A8; with A10
defining auto precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a PRECHARGE command to determine if
all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).
The address inputs also provide the op-code during a LOAD MODE REGISTER
command.
Data Input/Output: Data bus
F3
CKE
Input
G9
CS#
Input
F7, F8, F9
E8, F1
CAS#, RAS#,
WE#
LDQM,
UDQM
Input
Input
G7, G8
BA0, BA1
Input
H7, H8, J8, J7, J3, J2,
H3, H2, H1, G3, H9, G2,G1
A0–A12
Input
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
E2,
A7, B3, C7, D3
A3, B7, C3, D7,
A9, E7, J9
A1, E3, J1
DQ0–DQ15
I/O
NC
V
DD
Q
V
SS
Q
V
DD
V
SS
–
Supply
Supply
Supply
Supply
No Connect: This pin should be left unconnected.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Power Supply: Voltage dependant on option.
Ground.
256Mb: x16 Mobile SDRAM
MobileRamY26L_A.p65 – Pub. 5/02
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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