HD74AC174
Hex D-Type Flip-Flop with Master Reset
REJ03D0256–0200Z
(Previous ADE-205-376 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register.
The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a
Master Reset to simultaneously clear all flip-flops.
Features
•
Outputs Source/Sink 24 mA
•
Ordering Information
Part Name
HD74AC174FPEL
HD74AC174RPEL
Package Type
SOP-16 pin (JEITA)
Package Code Package Abbreviation Taping Abbreviation (Quantity)
FP-16DAV
FP
RP
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
MR
1
Q
0
2
D
0
3
D
1
4
Q
1
5
D
2
6
Q
2
7
GND 8
(Top view)
16 V
CC
15 Q
5
14 D
5
13 D
4
12 Q
4
11 D
3
10 Q
3
9 CP
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC174
Logic Symbol
D
0
D
1
D
2
CP
MR
D
3
D
4
D
5
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Pin Names
D
0
to D
5
CP
MR
Q
0
to Q
5
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
Functional Description
The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP)
and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-
flops’s output following the Low-to-High Clock (CP) transition. A Low input to the Master Reset (MR) will force all
outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output
only is required and the Clock and Master Reset are common to all storage elements.
Truth Table
MR
L
H
H
H
H :
L :
X :
:
High Voltage Level
Low Voltage Level
Immaterial
Low-to-High Transition of Clock
X
Inputs
CP
X
H
L
X
D
L
H
L
Q
Output
Q
L
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC174
Logic Diagram
MR
CP D
5
D
4
D
3
D
2
D
1
D
0
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CD
CP
CD
CP
CD
CP
CD
CP
CD
CP
CD
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
Condition
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Recommended Operating Conditions
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
30% to 70% V
CC
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 3.0V
V
CC
= 4.5 V
V
CC
= 5.5 V
Unit
Condition
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC174
DC Characteristics
Item
Sym-
bol
V
IH
Vcc
(V)
3.0
4.5
5.5
V
IL
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
V
OL
5.5
3.0
4.5
5.5
3.0
4.5
Input leakage
current
Dynamic output
current*
Quiescent supply
current
I
IN
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.58
3.94
4.94
—
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
0.002
0.001
0.001
—
—
—
—
—
—
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.32
0.32
0.32
±0.1
—
—
8.0
Ta = –40 to
+85°C
°
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
—
—
86
–75
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
80
µA
mA
mA
µA
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Unit
Condition
Input Voltage
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Output voltage
V
OH
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
or V
IH
I
OH
= –12 mA
I
OH
= –24 mA
I
OH
= –24 mA
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
IN
= V
CC
or GND
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
*Maximum
test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC174
Ta = +25°C
C
L
= 50 pF
Min
Typ
Max
90
100
1.0
1.0
1.0
1.0
1.0
1.0
100
125
9.0
6.0
8.5
6.0
9.0
7.0
—
—
11.5
8.5
11.0
8.0
11.5
9.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
Max
70
100
1.0
1.0
1.0
1.0
1.0
1.0
—
—
12.5
9.5
12.0
9.0
12.5
10.5
MHz
ns
ns
ns
Item
Maximum clock
frequency
Propagation delay
CP to Q
n
Propagation delay
CP to Q
n
Propagation delay
MR
to Q
n
Note:
Symbol
f
max
t
PLH
t
PHL
t
PHL
V
CC
(V)*
1
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Unit
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC174
AC Operating Requirements: HD74AC174
Ta = +25°C
C
L
= 50 pF
Item
Setup time, HIGH or LOW
D
n
to CP
Hold time, HIGH or LOW
D
n
to CP
MR
pulse width, LOW
CP pulse width
Recovery time
MR
to CP
Note:
Symbol V
CC
(V)*
1
Typ
t
su
3.3
2.5
t
h
t
w
t
w
t
rec
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.0
1.0
0.5
1.0
1.0
1.0
1.0
0
0
Ta = –40°C
to +85°C
C
L
= 50 pF
Unit
ns
ns
ns
ns
ns
Guaranteed Minimum
6.5
7.0
5.0
3.0
3.0
5.5
5.0
5.5
5.0
2.5
2.0
5.5
3.0
3.0
7.0
5.0
7.0
5.0
2.5
2.0
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item
Input capacitance
Power dissipation capacitance
Symbol
C
IN
C
PD
4.5
85.0
Typ
pF
pF
Unit
V
CC
= 5.5 V
V
CC
= 5.0 V
Condition
Rev.2.00, Jul.16.2004, page 5 of 7
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