HD74AC166/HD74ACT166
8-bit Shift Register
REJ03D0255–0200Z
(Previous ADE-205-375 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type
flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An
asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources
or one CP input can be used to trigger the other.
Features
•
Outputs Source/Sink 24 mA
•
HD74ACT166 has TTL-Compatible Inputs
•
Ordering Information: Ex. HD74AC166
Part Name
Package Type
Package Code Package Abbreviation Taping Abbreviation (Quantity)
FP-16DAV
TTP-16DAV
FP
RP
T
EL (2,000 pcs/reel)
EL (2,500 pcs/reel)
ELL(2,000 pcs/reel)
HD74AC166AFPEL SOP-16 pin (JEITA)
HD74AC166TELL
TSSOP-16 pin
HD74AC166ARPEL SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
D
S
1
P
0
2
P
1
3
P
2
4
P
3
5
CP
2
6
CP
1
7
GND 8
(Top view)
16 V
CC
15
PE
14 P
7
13 Q
7
12 P
6
11 P
5
10 P
4
9
MR
Rev.2.00, Jul.16.2004, page 1 of 8
HD74AC166/HD74ACT166
Logic Symbol
15
2
3
4
5
10 11 12 14
PE P
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
1
7
6
1
2
D
S
CP
MR
Q
7
9
13
V
CC
=Pin16
GND=Pin8
Pin Names
CP
1
, CP
2
D
S
PE
P
0
to P
7
MR
Q
7
Clock Pulse Inputs (Active Rising Edge)
Serial Data Input
Parallel Enable Input (Active Low)
Parallel Data Inputs
Asynchronous Master Reset Input (Active Low)
Last Stage Output
Functional Description
Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock
input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should
attain the High state while the other clock is still in the High state following the previous operation. When the Parallel
Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P
0
to P
7
) inputs on the next rising edge
of the clock. When
PE
is High, information is shifted from the Serial Data (D
S
) input to Q
0
and all data in the register is
shifted one bit position (i.e., Q
0
→
Q
1
, Q
1
→
Q
2
, etc.) on the rising edge of the clock.
Truth Table
Inputs
MR
L
H
H
H
H
H
H :
L :
X :
:
X
X
L
H
H
X
PE
X
L
L
L
L
H
CP
2
X
L
CP
1
X
X
X
H
L
X
D
S
Parallel
P
0
to P
7
X
X
a ··· h
X
X
X
L
Q
A0
a
H
L
Q
A0
Internal Outputs
Q
0
Q
6
L
Q
B0
b
Q
An
Q
An
Q
B0
L
Q
H0
h
Q
Gn
Q
Gn
Q
H0
Output
Q
7
High Voltage Level
Low Voltage Level
Immaterial
Low-to-High Clock Transition
Rev.2.00, Jul.16.2004, page 2 of 8
HD74AC166/HD74ACT166
Logic Diagram
P
0
D
S
P
1
P
2
P
3
P
4
P
5
P
6
MR
P
7
PE
CP
1 2
R CP S
C
D
Q
R CP S
C
D
Q
Q
7
Absolute Maximum Ratings
Item
Supply voltage
DC input diode current
DC input voltage
DC output diode current
DC output voltage
DC output source or sink current
DC V
CC
or ground current per output pin
Storage temperature
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
Tstg
Ratings
–0.5 to 7
–20
20
–0.5 to Vcc+0.5
–50
50
–0.5 to Vcc+0.5
±50
±50
–65 to +150
Unit
V
mA
mA
V
mA
mA
V
mA
mA
°C
V
I
= –0.5V
V
I
= Vcc+0.5V
V
O
= –0.5V
V
O
= Vcc+0.5V
Condition
Recommended Operating Conditions: HD74AC166
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
30% to 70% V
CC
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 3.0V
V
CC
= 4.5 V
V
CC
= 5.5 V
Unit
Condition
Rev.2.00, Jul.16.2004, page 3 of 8
HD74AC166/HD74ACT166
DC Characteristics: HD74AC166
Item
Sym-
bol
V
IH
Vcc
(V)
3.0
4.5
5.5
V
IL
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
V
OL
5.5
3.0
4.5
5.5
3.0
4.5
Input leakage
current
Dynamic output
current*
Quiescent supply
current
I
IN
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.58
3.94
4.94
—
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
2.25
2.75
1.50
2.25
2.75
2.99
4.49
5.49
—
—
—
0.002
0.001
0.001
—
—
—
—
—
—
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.32
0.32
0.32
±0.1
—
—
8.0
Ta = –40 to
+85°C
°
min.
2.1
3.15
3.85
—
—
—
2.9
4.4
5.4
2.48
3.80
4.80
—
—
—
—
—
—
—
86
–75
—
max.
—
—
—
0.9
1.35
1.65
—
—
—
—
—
—
0.1
0.1
0.1
0.37
0.37
0.37
±1.0
—
—
80
µA
mA
mA
µA
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Unit
Condition
Input Voltage
V
V
OUT
= 0.1 V or V
CC
–0.1 V
Output voltage
V
OH
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
or V
IH
I
OH
= –12 mA
I
OH
= –24 mA
I
OH
= –24 mA
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
or V
IH
I
OL
= 12 mA
I
OL
= 24 mA
I
OL
= 24 mA
V
IN
= V
CC
or GND
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
*Maximum
test duration 2.0 ms, one output loaded at a time.
Recommended Operating Conditions: HD74ACT166
Item
Supply voltage
Input and output voltage
Operating temperature
Input rise and fall time
(except Schmitt inputs)
V
IN
0.8 to 2.0 V
Symbol
V
CC
V
I
, V
O
Ta
tr, tf
2 to 6
0 to V
CC
–40 to +85
8
Ratings
V
V
°C
ns/V
V
CC
= 4.5V
V
CC
= 5.5V
Unit
Condition
Rev.2.00, Jul.16.2004, page 4 of 8
HD74AC166/HD74ACT166
DC Characteristics: HD74ACT166
Item
Sym-
bol
V
IH
V
IL
Output voltage
V
OH
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
V
OL
5.5
4.5
5.5
4.5
Input current
I
CC
/input current
Dynamic output
current*
Quiescent supply
current
I
IN
I
CCT
I
OLD
I
OHD
I
CC
5.5
5.5
5.5
5.5
5.5
5.5
min.
2.0
2.0
—
—
4.4
5.4
3.94
4.94
—
—
—
—
—
—
—
—
—
Ta = 25°C
°
typ.
1.5
1.5
1.5
1.5
4.49
5.49
—
—
0.001
0.001
—
—
—
0.6
—
—
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.32
0.32
±0.1
—
—
—
8.0
Ta = –40 to
+85°C
°
min.
2.0
2.0
—
—
4.4
5.4
3.80
4.80
—
—
—
—
—
—
86
–75
—
max.
—
—
0.8
0.8
—
—
—
—
0.1
0.1
0.37
0.37
±1.0
1.5
—
—
80
µA
mA
mA
mA
µA
V
Unit
Condition
Input voltage
V
V
OUT
= 0.1 V or Vcc–0.1 V
V
OUT
= 0.1 V or Vcc–0.1 V
V
IN
= V
IL
or V
IH
I
OUT
= –50
µA
V
IN
= V
IL
V
IN
= V
IL
or V
IH
I
OUT
= 50
µA
V
IN
= V
IL
V
IN
= V
CC
or GND
V
IN
= V
CC
–2.1 V
V
OLD
= 1.1 V
V
OHD
= 3.85 V
V
IN
= V
CC
or ground
I
OL
= 24 mA
I
OL
= 24 mA
I
OH
= –24 mA
I
OH
= –24 mA
*Maximum
test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC166
Ta = +25°C
C
L
= 50 pF
Item
Maximum clock
frequency
Propagation delay
CP
1
or CP
2
to Q
7
Propagation delay
CP
1
or CP
2
to Q
7
Propagation delay
MR
to Q
7
Note:
Symbol
f
max
t
PLH
t
PHL
t
PHL
V
CC
(V)*
1
Min
3.3
75
5.0
3.3
5.0
3.3
5.0
3.3
5.0
100
1.0
1.0
1.0
1.0
1.0
1.0
Typ
—
—
11.0
9.5
10.5
9.0
9.5
6.5
Max
—
—
14.5
11.5
14.0
11.0
12.0
9.0
Ta = –40°C to +85°C
C
L
= 50 pF
Min
65
80
1.0
1.0
1.0
1.0
1.0
1.0
—
—
15.5
12.5
15.0
12.0
13.0
10.0
Max
MHz
ns
Unit
1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8
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