INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT166
8-bit parallel-in/serial-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
FEATURES
•
Synchronous parallel-to-serial applications
•
Synchronous serial data input for easy expansion
•
Clock enable for “do nothing” mode
•
Asynchronous master reset
•
For asynchronous parallel data load see “165”
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT166 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT166 are 8-bit shift registers which have a
fully synchronous serial or parallel data entry selected by
74HC/HCT166
an active LOW parallel enable (PE) input. When PE is
LOW one set-up time prior to the LOW-to-HIGH clock
transition, parallel data is entered into the register. When
PE is HIGH, data is entered into the internal bit position Q
0
from serial data input (D
s
), and the remaining bits are
shifted one place to the right (Q
0
→
Q
1
→
Q
2
, etc.) with
each positive-going clock transition.
This feature allows parallel-to-serial converter expansion
by tying the Q
7
output to the D
s
input of the succeeding
stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take place
while CP is HIGH for predictable operation. A LOW on the
master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all bit positions
to a LOW state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
CP to Q
7
MR to Q
7
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
15
14
63
3.5
41
20
19
50
3.5
41
ns
ns
MHz
pF
pF
HCT
UNIT
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
PIN DESCRIPTION
PIN NO.
1
2, 3, 4, 5, 10, 11, 12, 14
6
7
8
9
13
15
16
SYMBOL
D
s
D
0
to D
7
CE
CP
GND
MR
Q
7
PE
V
CC
NAME AND FUNCTION
serial data input
parallel data inputs
clock enable input (active LOW)
74HC/HCT166
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
OPERATING MODES
PE
parallel load
serial shift
hold “do nothing”
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑
= LOW-to-HIGH CP transition
I
I
h
h
X
I
I
I
I
h
CE
↑
↑
↑
↑
X
CP
X
X
I
h
X
D
S
D
0
-D
7
I-I
h-h
X-X
X-X
X-X
L
H
L
H
q
0
Q
n
REGISTER
Q
0
Q
1
-Q
6
L-L
H-H
q
0
- q
5
q
0
- q
5
q
1
- q
6
OUTPUT
Q
7
L
H
q
6
q
6
q
7
December 1990
4
FPGA/CPLD
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