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L-FW32206T100: 产品描述Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小911KB，共86页; 制造商LSC/CSI; 官网地址https://lsicsi.com; 标准

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L-FW32206T100概述

Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

L-FW32206T100规格参数

参数名称	属性值
是否无铅	不含铅
是否Rohs认证	符合
厂商名称	LSC/CSI
零件包装代码	QFP
包装说明	LFQFP, QFP100,.63SQ,20
针数	100
Reach Compliance Code	compliant
地址总线宽度	32
边界扫描	NO
总线兼容性	PCI
最大时钟频率	24.5785 MHz
最大数据传输速率	50 MBps
外部数据总线宽度	32
JESD-30 代码	S-PQFP-G100
JESD-609代码	e3
长度	14 mm
低功率模式	YES
串行 I/O 数	2
端子数量	100
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装等效代码	QFP100,.63SQ,20
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260
电源	3.3 V
认证状态	Not Qualified
座面最大高度	1.6 mm
最大供电电压	3.6 V
最小供电电压	3 V
标称供电电压	3.3 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Matte Tin (Sn)
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	40
宽度	14 mm
uPs/uCs/外围集成电路类型	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1

文档解析

这份文档是关于FW322 06 T100 1394a PCI PHY/Link Open Host Controller的数据手册，包含了大量的技术信息，以下是一些值得关注的要点：

产品特性：
- 支持1394a-2000 OHCI链路和物理层核心功能。
- 提供100针TQFP封装，也提供无铅封装选项。
- 支持高速串行总线IEEE 1394a-2000标准，包括400 Mbps、200 Mbps和100 Mbps的数据传输速率。
- 兼容微软Windows操作系统和MacOS。
OHCI核心：
- 符合1394 OHCI 1.1规范，兼容OHCI 1.0。
- 支持高达4 Kbyte的等时和非等时传输FIFO。
- 具备独立的等时和非等时描述符基DMA引擎。
1394a-2000 PHY核心：
- 符合IEEE 1394a-2000标准，支持高性能串行总线。
- 提供两个完全符合标准的电缆端口，每个端口支持不同的数据传输速率。
PCI接口：
- 符合PCI 2.2规范，以33 MHz/32位操作。
- 支持PCI电源管理接口规范1.1版本。
功能性描述：
- 包括PCI核心、OHCI等时和非等时数据传输、链路核心以及物理层核心的详细描述。
内部寄存器：
- 提供了内部寄存器的详细描述，这些寄存器用于控制和监视设备的操作状态。
电气特性：
- 包括供电电压、输入电压范围、输出电压范围以及工作温度范围等。
时序特性：
- 提供了关于数据传输和信号完整性的重要时序参数。
外形尺寸图：
- 提供了100-Pin TQFP封装的详细尺寸图。
订购信息：
- 提供了产品的订购代码和封装类型。
环境和安全标准：
- 符合RoHS指令，限制电子设备中六种有害物质的含量。
版权和联系信息：
- 文档最后提供了版权声明和Agere Systems公司的联系方式。

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Data Sheet, Rev. 2

October 2006

™

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Features

1394a-2000 OHCI link and PHY core function in a sin-

gle device:

— 100-pin TQFP package (also available in a lead-free

package; see ordering information on page 85)

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card designs

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current

Microsoft

Windows

drivers and common applications

— Demonstrated interoperability with existing, as well

as older, 1394 consumer electronics and peripherals

products

— Feature-rich implementation for high performance in

common applications

— Supports low-power system designs (CMOS imple-

mentation, power management features)

OHCI:

— Complies with the

1394 OHCI 1.1 Specification

— OHCI 1.0 backwards compatible—configurable via

EEPROM to operate in either OHCI 1.0 or OHCI 1.1

mode

— Complies with

Microsoft Windows

logo program

system and device requirements

— Listed on

Windows

hardware compatibility list

http://www.microsoft.com/hcl/results.asp

— Compatible with

Microsoft Windows

and

MacOS

operating systems

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asynchronous receive FIFO

— Dedicated asynchronous and isochronous

descriptor-based DMA engines

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

— Supports parallel processing of incoming physical

read and write requests

— Supports notification (via interrupt) of a failed

— Information normally in the EEPROM can be pro-

grammed into the system BIOS.

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000,

Standard for a

High Performance Serial Bus

(Supplement)

— Provides two fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders

— While unpowered and connected to the bus, will not

drive TPBIAS on a connected port even if receiving

incoming bias voltage on that port

— Does not require external filter capacitor for PLL

— Supports link-on as a part of the internal

PHY core-link interface

— 25 MHz crystal oscillator and internal PLL provide a

50 MHz

internal

link-layer controller clock as well

transmit/receive data at 100 Mbits/s, 200 Mbits/s,

and 400 Mbits/s.

— Interoperable across 1394 cable with 1394 physical

layers (PHY core) using 5 V supplies

— Provides node power-class information signaling for

system power management

— Supports ack-accelerated arbitration and fly-by

concatenation

— Supports arbitrated short bus reset to improve

utilization of the bus

— Fully supports suspend/resume

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

packets

— Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V

Link:

— Cycle master and isochronous resource manager

capable

— Supports 1394a-2000 acceleration features

PCI:

— Revision 2.2 compliant

— 33 MHz/32-bit operation

— Programmable burst size thresholds for PCI data

transfer

— Supports optimized memory read line, memory read

multiple, and memory write invalidate burst

commands

— Supports

PCI Bus Power Management Interface

Specification

v.1.1.

Note:

This device does not support D3cold wakeup,

CLKRUN protocol,

Mini PCI

applications, and

CardBus applications. Use the FW322 06 120-

pin TQFP device if one or more of these

features are needed.

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 2

October 2006

Table of Contents

Contents

Page

Features .................................................................................................................................................................. 1

Other Features ................................................................................................................................................... 6

FW322 Functional Overview ................................................................................................................................... 6

FW322 Functional Description ................................................................................................................................ 7

PCI Core ............................................................................................................................................................ 7

OHCI Data Transfer ........................................................................................................................................... 8

OHCI Isochronous Data Transfer ...................................................................................................................... 8

Isochronous Register Access ............................................................................................................................ 9

OHCI Asynchronous Data Transfer ................................................................................................................... 9

Asynchronous Register Access ......................................................................................................................... 9

Link Core.......................................................................................................................................................... 11

PHY Core ......................................................................................................................................................... 13

Pin Information ...................................................................................................................................................... 15

Internal Registers .................................................................................................................................................. 21

PCI Configuration Registers ............................................................................................................................ 21

Vendor ID Register .......................................................................................................................................... 22

Device ID Register ........................................................................................................................................... 22

PCI Command Register ................................................................................................................................... 23

PCI Status Register ......................................................................................................................................... 24

Class Code and Revision ID Registers ............................................................................................................ 25

Latency Timer and Cache Line Size Register.................................................................................................. 25

Header Type and BIST Register ...................................................................................................................... 26

OHCI Base Address Register .......................................................................................................................... 26

PCI Subsystem Identification Register............................................................................................................. 27

PCI Power Management Capabilities Pointer Register.................................................................................... 27

Interrupt Line and Pin Register ........................................................................................................................ 28

MIN_GNT and MAX_LAT Register .................................................................................................................. 28

PCI OHCI Control Register .............................................................................................................................. 29

Capability ID and Next Item Pointer Register .................................................................................................. 29

Power Management Capabilities Register ....................................................................................................... 30

Power Management Control and Status Register............................................................................................ 31

Power Management CSR PCI-to-PCI Bridge Support Extensions .................................................................. 32

Power Management Data ................................................................................................................................ 32

OHCI Registers ................................................................................................................................................ 33

OHCI Version Register .................................................................................................................................... 36

GUID ROM Register ........................................................................................................................................ 37

Asynchronous Transmit Retries Register......................................................................................................... 37

CSR Data Register .......................................................................................................................................... 38

CSR Compare Register ................................................................................................................................... 38

CSR Control Register ...................................................................................................................................... 38

Configuration ROM Header Register ............................................................................................................... 39

Bus Identification Register ............................................................................................................................... 40

Bus Options Register ....................................................................................................................................... 40

GUID High Register ......................................................................................................................................... 41

GUID Low Register .......................................................................................................................................... 41

Configuration ROM Mapping Register ............................................................................................................. 42

Posted Write Address Low Register ................................................................................................................ 43

Posted Write Address High Register ............................................................................................................... 43

Vendor ID Register .......................................................................................................................................... 43

Host Controller Control Register ...................................................................................................................... 44

SelfID Buffer Pointer Register .......................................................................................................................... 46

Agere Systems Inc.

Data Sheet, Rev. 2

October 2006

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Table of Contents

Contents

Page

SelfID Count Register ...................................................................................................................................... 46

Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register ........................................ 47

Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register ........................................ 47

Interrupt Event (IntEvent) Register................................................................................................................... 48

Interrupt Mask (IntMask) Register.................................................................................................................... 50

Isochronous Transmit Interrupt Event (isoXmitIntMask) Register.................................................................... 52

Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register .................................................................... 53

Isochronous Receive Interrupt Event (isoRecvIntEvent) Register ................................................................... 54

Isochronous Receive Interrupt Mask (isoRecvIntMask) Register .................................................................... 55

Fairness Control Register ................................................................................................................................ 55

Link Control Register........................................................................................................................................ 56

Node Identification Register ............................................................................................................................. 57

PHY Core Layer Control Register .................................................................................................................... 58

Isochronous Cycle Timer Register ................................................................................................................... 58

Asynchronous Request Filter High Register .................................................................................................... 59

Asynchronous Request Filter Low Register ..................................................................................................... 59

Physical Request Filter High Register.............................................................................................................. 60

Physical Request Filter Low Register .............................................................................................................. 60

Asynchronous Context Control Register .......................................................................................................... 61

Asynchronous Context Command Pointer Register......................................................................................... 62

Isochronous Transmit Context Control (IT DMA ContextControl) Register...................................................... 63

Isochronous Transmit Context Command Pointer Register............................................................................. 64

Isochronous Receive Context Control (IR DMA ContextControl) Register ...................................................... 65

Isochronous Receive Context Command Pointer Register.............................................................................. 66

Isochronous Receive Context Match (IR DMA ContextMatch) Register.......................................................... 67

FW322 Vendor-Specific Registers ................................................................................................................... 68

Isochronous DMA Control ................................................................................................................................ 68

Asynchronous DMA Control............................................................................................................................. 69

Link Options ..................................................................................................................................................... 70

Internal Register Configuration .............................................................................................................................. 71

PHY Core Register Map................................................................................................................................... 71

PHY Core Register Fields ................................................................................................................................ 72

Crystal Selection Considerations ........................................................................................................................... 77

Load Capacitance ............................................................................................................................................ 77

Adjustment to Crystal Loading ......................................................................................................................... 77

Crystal/Board Layout........................................................................................................................................ 77

Serial EEPROM Interface ...................................................................................................................................... 78

ac Characteristics of Serial EEPROM Interface Signals ....................................................................................... 78

Solder Reflow and Handling .................................................................................................................................. 81

Absolute Maximum Voltage/Temperature Ratings ................................................................................................ 81

Electrical Characteristics ....................................................................................................................................... 82

Timing Characteristics ........................................................................................................................................... 84

Outline Diagrams ................................................................................................................................................... 85

100-Pin TQFP .................................................................................................................................................. 85

Ordering Information .............................................................................................................................................. 85

Agere Systems Inc.

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 2

October 2006

Table of Contents

(continued)

Figure

Page

Figure 1. FW322 Conceptual Block Diagram .......................................................................................................... 6

Figure 2. PCI Core Block Diagram .......................................................................................................................... 7

Figure 3. OHCI Core Block Diagram ....................................................................................................................... 8

Figure 4 . Link Core Block Diagram ....................................................................................................................... 11

Figure 5. The PHY Core Block Diagram ................................................................................................................ 12

Figure 6. Pin Assignments for the FW322 06 T100 ............................................................................................... 15

Figure 7. Crystal Circuitry ...................................................................................................................................... 77

Figure 8. Bus Timing ............................................................................................................................................. 79

Figure 9. Write Cycle Timing ................................................................................................................................. 79

Figure 10. Data Validity ......................................................................................................................................... 79

Figure 11. Start and Stop Definition ...................................................................................................................... 80

Figure 12. Output Acknowledge ............................................................................................................................ 80

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 16

Table 2. Bit-Field Access Tag Description ............................................................................................................. 21

Table 3. PCI Configuration Register Map ............................................................................................................. 21

Table 4. PCI Command Register Description ........................................................................................................ 23

Table 5. PCI Status Register ................................................................................................................................. 24

Table 6. Class Code and Revision ID Register Description .................................................................................. 25

Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 25

Table 8. Header Type and BIST Register Description .......................................................................................... 26

Table 9. OHCI Base Address Register Description ............................................................................................... 26

Table 10. PCI Subsystem Identification Register Description ............................................................................... 27

Table 11. Interrupt Line and Pin Register Description ........................................................................................... 28

Table 12. MIN_GNT and MAX_LAT Register Description ..................................................................................... 28

Table 13. PCI OHCI Control Register Description ................................................................................................. 29

Table 14. Capability ID and Next Item Pointer Register Description ..................................................................... 29

Table 15. Power Management Capabilities Register Description ......................................................................... 30

Table 16. Power Management Control and Status Register Description .............................................................. 31

Table 17. Power Management Data Register Description .................................................................................... 32

Table 18. OHCI Register Map ............................................................................................................................... 33

Table 19. OHCI Version Register Description ....................................................................................................... 36

Table 20. GUID ROM Register Description ........................................................................................................... 37

Table 21. Asynchronous Transmit Retries Register Description ........................................................................... 37

Table 22. CSR Data Register Description ............................................................................................................. 38

Table 23. CSR Compare Register Description ...................................................................................................... 38

Table 24. CSR Control Register Description ........................................................................................................ 38

Table 25. Configuration ROM Header Register Description ................................................................................. 39

Table 26. Bus Identification Register Description .................................................................................................. 40

Table 27. Bus Options Register Description .......................................................................................................... 40

Table 28. GUID High Register Description ............................................................................................................ 41

Table 29. GUID Low Register Description ............................................................................................................. 41

Table 30. Configuration ROM Mapping Register Description ................................................................................ 42

Table 31. Posted Write Address Low Register Description ................................................................................... 43

Table 32. Posted Write Address High Register Description .................................................................................. 43

Table 33. Vendor ID Register Description ............................................................................................................. 43

Table 34. Host Controller Control Register Description ......................................................................................... 44

Table 35. SelfID Buffer Pointer Register Description ............................................................................................ 46

Table 36. SelfID Count Register Description ......................................................................................................... 46

Agere Systems Inc.

Data Sheet, Rev. 2

October 2006

FW322 06 T100

1394a PCI PHY/Link Open Host Controller

Table of Contents

Table

Page

Table 37. Isochronous Receive Channel Mask High Register Description ........................................................... 47

Table 38. Isochronous Receive Channel Mask Low Register Description ............................................................ 47

Table 39. Interrupt Event Register Description ...................................................................................................... 48

Table 40. Interrupt Mask Register Description ...................................................................................................... 50

Table 41. Isochronous Transmit Interrupt Event Register Description .................................................................. 52

Table 42. Isochronous Transmit Interrupt Event Description ................................................................................ 53

Table 43. Isochronous Receive Interrupt Event Description ................................................................................. 54

Table 44. Fairness Control Register Description ................................................................................................... 55

Table 45. Link Control Register Description ......................................................................................................... 56

Table 46. Node Identification Register Description ............................................................................................... 57

Table 47. PHY Core Layer Control Register Description ...................................................................................... 58

Table 48. Isochronous Cycle Timer Register Description ..................................................................................... 58

Table 49. Asynchronous Request Filter High Register Description ....................................................................... 59

Table 50. Asynchronous Request Filter Low Register Description ....................................................................... 59

Table 51. Physical Request Filter High Register Description ................................................................................ 60

Table 52. Physical Request Filter Low Register Description ................................................................................. 60

Table 53. Asynchronous Context Control Register Description ........................................................................... 61

Table 54. Asynchronous Context Command Pointer Register Description ........................................................... 62

Table 55. Isochronous Transmit Context Control Register Description ................................................................ 63

Table 56. Isochronous Transmit Context Command Pointer Register Description ............................................... 64

Table 57. Isochronous Receive Context Control Register Description .................................................................. 65

Table 58. Isochronous Receive Context Command Pointer Register Description ................................................ 66

Table 59. Isochronous Receive Context Match Register Description ................................................................... 67

Table 60. FW322 Vendor-Specific Registers Description ..................................................................................... 68

Table 61. Isochronous DMA Control Registers Description .................................................................................. 68

Table 62. Asynchronous DMA Control Registers Description ............................................................................... 69

Table 63. Link Options Register Description ......................................................................................................... 70

Table 64. PHY Core Register Map ........................................................................................................................ 71

Table 65. PHY Core Register Fields ..................................................................................................................... 72

Table 66. PHY Core Register Page 0: Port Status Page ...................................................................................... 74

Table 67. PHY Core Register Port Status Page Fields ........................................................................................ 75

Table 68. PHY Core Register Page 1: Vendor Identification Page ....................................................................... 76

Table 69. PHY Core Register Vendor Identification Page Fields .......................................................................... 76

Table 70. ac Characteristics of Serial EEPROM Interface Signals ....................................................................... 78

Table 71. Absolute Maximum Ratings ................................................................................................................... 81

Table 72. Analog Characteristics ........................................................................................................................... 82

Table 73. Driver Characteristics ............................................................................................................................ 83

Table 74. Device Characteristics ........................................................................................................................... 83

Table 75. Switching Characteristics ...................................................................................................................... 84

Table 76. Clock Characteristics ............................................................................................................................. 84

Agere Systems Inc.

L-FW32206T100相似产品对比

	L-FW32206T100	FW32206T100
描述	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, TQFP-100
是否无铅	不含铅	含铅
是否Rohs认证	符合	不符合
厂商名称	LSC/CSI	LSC/CSI
零件包装代码	QFP	QFP
包装说明	LFQFP, QFP100,.63SQ,20	LFQFP, QFP100,.63SQ,20
针数	100	100
Reach Compliance Code	compliant	compliant
地址总线宽度	32	32
边界扫描	NO	NO
总线兼容性	PCI	PCI
最大时钟频率	24.5785 MHz	24.5785 MHz
最大数据传输速率	50 MBps	50 MBps
外部数据总线宽度	32	32
JESD-30 代码	S-PQFP-G100	S-PQFP-G100
JESD-609代码	e3	e0
长度	14 mm	14 mm
低功率模式	YES	YES
串行 I/O 数	2	2
端子数量	100	100
最高工作温度	70 °C	70 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFQFP	LFQFP
封装等效代码	QFP100,.63SQ,20	QFP100,.63SQ,20
封装形状	SQUARE	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260	225
电源	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm
最大供电电压	3.6 V	3.6 V
最小供电电压	3 V	3 V
标称供电电压	3.3 V	3.3 V
表面贴装	YES	YES
技术	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL
端子面层	Matte Tin (Sn)	TIN LEAD
端子形式	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm
端子位置	QUAD	QUAD
处于峰值回流温度下的最长时间	40	30
宽度	14 mm	14 mm
uPs/uCs/外围集成电路类型	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches	1	1

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器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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