Revision 8
ProASIC3 nano Flash FPGAs
Features and Benefits
Wide Range of Features
• 10 k to 250 k System Gates
• Up to 36 kbits of True Dual-Port SRAM
• Up to 71 User I/Os
®
Advanced I/Os
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V
• Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
• I/O Registers on Input, Output, and Enable Paths
• Selectable Schmitt Trigger Inputs
• Hot-Swappable and Cold-Sparing I/Os
• Programmable Output Slew Rate
†
and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the ProASIC3 Family
†
• Up to Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
High Performance
• 350 MHz System Performance
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
†
• FlashLock
®
to Secure FPGA Contents
Clock Conditioning Circuit (CCC) and PLL
Low Power
•
•
•
•
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory
• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
†
• True Dual-Port SRAM (except ×18 organization)
†
Low Power ProASIC 3 nano Products
1.5 V Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
®
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
Enhanced Commercial Temperature Range
• –20°C to +70°C
Table 1 • ProASIC3 nano Devices
ProASIC3 nano Devices
ProASIC3 nano-Z Devices
System Gates
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
RAM Kbits (1,024 bits)
2
4,608-Bit Blocks
2
FlashROM Kbits
Secure (AES) ISP
2
Integrated PLL in CCCs
2
VersaNet Globals
I/O Banks
Maximum User I/Os (packaged device)
Maximum User I/Os (Known Good Die)
Package Pins
QFN
VQFP
10,000
86
260
–
–
1
–
–
4
2
34
34
QN48
15,000
128
384
–
–
1
–
–
4
3
49
–
QN68
20,000
172
520
–
–
1
–
–
4
3
49
52
QN68
A3PN010
A3PN015
A3PN020
A3PN030Z
1
30,000
256
768
–
–
1
–
–
6
2
77
83
QN48, QN68
VQ100
A3PN060
A3PN125
A3PN250
A3N250Z
250,000
2,048
6,144
36
8
1
Yes
1
18
4
68
68
A3PN060Z A3PN125Z
60,000
512
1,536
18
4
1
Yes
1
18
2
71
71
125,000
1,024
3,072
36
8
1
Yes
1
18
2
71
71
VQ100
VQ100
VQ100
Notes:
1. A3PN030 is available in the Z feature grade only.
2. A3PN030 and smaller devices do not support this feature.
3. For higher densities and support of additional features, refer to the
ProASIC3
and
ProASIC3E
datasheets.
† A3PN030 and smaller devices do not support this feature.
April 2010
© 2010 Actel Corporation
I
ProASIC3 nano Flash FPGAs
I/Os Per Package
ProASIC3 nano Devices
ProASIC3 nano-Z Devices
Known Good Die
QN48
QN68
VQ100
34
34
–
–
–
–
49
–
52
–
49
–
A3PN010
A3PN015
A3PN020
A3PN030Z
1
83
34
49
77
A3PN060
A3PN060
71
–
–
71
A3PN125
A3PN125Z
71
–
–
71
A3PN250
A3PN250Z
68
–
–
68
Notes:
1. A3PN030 is available in the Z feature grade only.
2. When considering migrating your design to a lower- or higher-density device, refer to the
ProASIC3 FPGA Fabric User’s Guide
to ensure compliance with design and board migration requirements.
3. "G" indicates RoHS-compliant packages. Refer to
"ProASIC3 nano Ordering Information" on page III
for the location of the "G"
in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other
packages are RoHS-compliant only.
Table 2 • ProASIC3 nano FPGAs Package Sizes Dimensions
Packages
Length × Width (mm\mm)
Nominal Area (mm2)
Pitch (mm)
Height (mm)
QN48
6x6
36
0.4
0.90
QN68
8x8
64
0.4
0.90
VQ100
14 x 14
196
0.5
1.20
ProASIC3 nano Device Status
ProASIC3 nano Devices
A3PN010
A3PN015
A3PN020
Status
Production
Production
Production
A3PN030Z
A3PN060
A3PN125
A3PN250
Advance
Advance
Production
A3PN060Z
A3PN125Z
A3PN250Z
Production
Advance
Advance
Production
ProASIC3 nano-Z Devices
Status
II
R ev i si o n 8
ProASIC3 nano Flash FPGAs
ProASIC3 nano Ordering Information
A3PN250
_
Z
1
VQ
G
100
I
Application (Temperature Range)
Blank = Commercial (
–
20°C to +70°C Ambient Temperature)
I = Industrial (
–
40°C to +85°C Ambient Temperature)
PP = Pre-Production
ES = Engineering Sample (Room Temperature Only)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G= RoHS-Compliant Packaging
Package Type
QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches)
VQ = Very Thin Quad Flat Pack (0.5 mm pitch)
DIELOT = Known Good Die
Speed Grade
Blank = Standard
1 = 15% Faster than Standard
2 = 25% Faster than Standard
Feature Grade
Z = nano devices without enhanced features
Blank = Standard
Part Number
ProASIC3 nano Devices
A3PN010 = 10,000 System Gates
A3PN015 = 15,000 System Gates
A3PN020 = 20,000 System Gates
A3PN030 = 30,000 System Gates
A3PN060 = 60,000 System Gates
A3PN125 = 125,000 System Gates
A3PN250 = 250,000 System Gates
*
Note:
*For the A3PN060, A3PN125, and A3PN250, the Z feature grade does not support the enhanced nano features of Schmitt
trigger input, cold-sparing, and hot-swap I/O capability. The A3PN030 Z feature grade does not support Schmitt trigger input.
For the VQ100, CS81, UC81, QN68, and QN48 packages, the Z feature grade and the N part number are not marked on the
device.
Device Marking
Actel normally topside marks the full ordering part number on each device. There are some exceptions to this, such as some of the
Z feature grade nano devices, the V2 designator for IGLOO devices, and packages where space is physically limited. Packages that
have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of the
device marking will be used that includes the required legal information and as much of the part number as allowed by character
limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such
as the I designator for Industrial Devices or the ES designator for Engineering Samples.
R e visi on 8
III
ProASIC3 nano Flash FPGAs
Figure 1
shows an example of device marking based on the AGL030V5-UCG81. The actual mark will vary by the device/package
combination ordered.
Device Name
(six characters)
Package
Wafer Lot #
ACTELXXX
AGL030YWW
UCG81XXXX
XXXXXXXX
Country of Origin
Date Code
Customer Mark
(if applicable)
Figure 1 •
Example of Device Marking for Small Form Factor Packages
ProASIC3 nano Product Available in the Z Feature Grade
Devices
Packages
A3PN030
QN48
QN68
VQ100
A3PN060
–
–
VQ100
A3PN125
–
–
VQ100
A3PN250
–
–
VQ100
Temperature Grade Offerings
ProASIC3 nano Devices
ProASIC3 nano-Z Devices
QN48
QN68
VQ100
C, I
–
–
–
C, I
–
–
C, I
–
A3PN010
A3PN015
A3PN020
A3PN030Z
1
C, I
C, I
C, I
A3PN060
A3PN060Z
–
–
C, I
A3PN125
A3PN125Z
–
–
C, I
A3PN250
A3PN250Z
–
–
C, I
Notes:
1. A3PN030 is available in the Z feature grade only.
2. C = Commercial temperature range: –20°C to 70°C ambient temperature
3. I = Industrial temperature range: –40°C to 85°C ambient temperature
Speed Grade and Temperature Grade Matrix
Temperature Grade
C
1
I
2
Std.
✓
✓
Notes:
1. C = Commercial temperature range: –20°C to 70°C ambient temperature.
2. I = Industrial temperature range: –40°C to 85°C ambient temperature.
Contact your local Actel representative for device availability:
http://www.actel.com/contact/default.aspx.
IV
R ev i si o n 8
ProASIC3 nano Flash FPGAs
Table of Contents
ProASIC3 nano Device Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
ProASIC3 nano DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59
Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Package Pin Assignments
48-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
68-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Actel Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Revision 8
V
嵌入式系统
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