Footprint Area, Profile (0.65 mm) and On-Resistance
Per Footprint Area
APPLICATIONS
D
Smart Batteries for Portable Devices
MICRO FOOT
Bump Side View
Backside View
G
1
S
2
5 4
S
2
Pin 1 Identifier
S
1
8901
xxx
G
2
6 3
G
1
Device Marking:
8901 = P/N Code
xxx = Date/Lot Traceability Code
G
2
S
2
S
1
1
2
S
1
Ordering Information: Si8901DB-T2—E3
P-Channel
ABSOLUTE MAXIMUM RATINGS (T
A
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Source1—Source2 Voltage
Gate-Source Voltage
Continuous Source1—Source2 Current (T
J
= 150_C)
a
Pulsed Source1—Source2 Current
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
Package Reflow Conditions
c
VPR
IR/Convection
T
A
= 25_C
T
A
= 85_C
T
A
= 25_C
T
A
= 85_C
Symbol
V
S1S2
V
GS
I
S1S2
I
SM
P
D
T
J
, T
stg
5 secs
Steady State
−20
"8
Unit
V
−4.4
−3.2
−30
1.7
0.8
−55
to 150
215
220
−3.5
−2.5
1
0.5
A
W
_C
THERMAL RESISTANCE RATINGS
Parameter
Maximum J
M i
Junction-to-Ambient
a
ti t A bi t
Maximum
Junction-to-Foot
b
t
v
5 sec
Steady State
Steady State
Symbol
R
thJA
R
thJF
Typical
60
95
18
Maximum
75
120
22
Unit
_C/W
C/W
Notes
a. Surface Mounted on 1” x 1” FR4 Board.
b. The Foot is defined as the top surface of the package.
c. Refer to IPC/JEDEC (J-STD-020A), no manual or hand soldering.
Document Number: 73126
S-41820—Rev. A, 11-Oct-04
www.vishay.com
1
Si8901DB
Vishay Siliconix
New Product
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Source Current
On-State Source Current
a
V
GS(th)
I
GSS
I
S1S2
I
S(on)
V
SS
= V
GS
, I
D
=
−350
mA
V
SS
= 0 V, V
GS
=
"8
V
V
SS
=
−20
V, V
GS
= 0 V
V
SS
=
−20
V, V
GS
= 0 V, T
J
= 85_C
V
SS
=
−5
V, V
GS
=
−4.5
V
V
GS
=
−4.5
V, I
SS
=
−1
A
Source1 Source2 On State
Source1—Source2 On-State Resistance
a
r
S1S2(on)
V
GS
=
−2.5
V, I
SS
=
−1
A
V
GS
=
−1.8
V, I
SS
=
−1
A
Forward Transconductance
a
g
fs
V
SS
=
−10
V, I
SS
=
−1
A
−5
0.048
0.062
0.081
7
0.060
0.080
0.105
S
W
−0.45
−1.0
"100
−1
−5
V
nA
mA
A
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
R
g
t
d(on)
t
r
t
d(off)
t
f
V
SS
=
−10
V, R
L
= 10
W
I
SS
^
−1
A, V
GEN
=
−4.5
V, R
g
= 6
W
9.5
13
27
120
65
20
40
180
100
ns
W
Notes
a. Pulse test; pulse width
v
300
ms,
duty cycle
v
2%.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
6 solder bumps are Eutetic 63Sn/37Pb with diameter 0.37
−
0.41 mm
Backside surface is coated with a Ag/Ni/Ti layer
Non-solder mask defined copper landing pad.
Laser marks on the silicon die back
e
e
D
s
MILLIMETERS*
Dim
A
A
1
A
2
b
D
E
e
s
INCHES
Min
0.0236
0.102
0.0134
0.0146
0.0598
0.0913
0.0295
0.0150
Min
0.600
0.260
0.340
0.370
1.52
2.32
0.750
0.380
Max
0.650
0.290
0.360
0.410
1.6
2.4
0.850
0.400
Max
0.0256
0.114
0.0142
0.0161
0.0630
0.0945
0.0335
0.0157
* Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and
Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see
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