Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
FEATURES
•
Wide supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
MultiByte flow-through standard pin-out architecture
•
Low inductance multiple V
CC
and GND pins for minimum
noise and ground bounce
•
Direct interface with TTL levels
•
Bus hold on data inputs (74ALVCH16244 only)
•
Output drive capability 50
Ω
transmission lines at 85
°C
•
Current drive
±24
mA at 3.0 V
•
Complies with JEDEC standard no. 8-1 A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETERS
propagation delay nAn to nYn
input capacitance
power dissipation capacitance per buffer
notes 1 and 2
outputs enabled
outputs disabled
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
CONDITIONS
V
CC
= 2.5 V; C
L
= 30 pF
V
CC
= 3.3 V; C
L
= 50 pF
DESCRIPTION
74ALVC16244;
74ALVCH16244
The 74ALVC16244; 74ALVCH16244 is a 16-bit
non-inverting buffer/line driver with 3-state outputs. The
device can be used as four 4-bit buffers, two 8-bit buffers
or one 16-bit buffer. The 3-state outputs are controlled by
the output enable inputs 1OE, 2OE, 3OE and 4OE. A
HIGH on nOE causes the outputs to assume a
high-impedance OFF-state.
The 74ALVCH16244 has active bus hold circuitry which is
provided to hold unused or floating data inputs at a valid
logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
The 74ALVC16244 has 5 V tolerant inputs.
TYPICAL
1.9
1.9
5.0
25
4
ns
ns
pF
pF
pF
UNIT
2003 May 14
2
Philips Semiconductors
Product specification
2.5 V/3.3 V 16-bit buffer/line driver
(3-state)
PINNING
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SYMBOL
1OE
1Y0
1Y1
GND
1Y2
1Y3
V
CC
2Y0
2Y1
GND
2Y2
2Y3
3Y0
3Y1
GND
3Y2
3Y3
V
CC
4Y0
4Y1
GND
4Y2
4Y3
4OE
DESCRIPTION
output enable input (active LOW)
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
data output
data output
ground (0 V)
data output
data output
supply voltage
data output
data output
ground (0 V)
data output
data output
output enable input (active LOW)
PIN
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
SYMBOL
3OE
4A3
4A2
GND
4A1
4A0
V
CC
3A3
3A2
GND
3A1
3A0
2A3
2A2
GND
2A1
2A0
V
CC
1A3
1A2
GND
1A1
1A0
2OE
74ALVC16244;
74ALVCH16244
DESCRIPTION
output enable input (active LOW)
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
data input
ground (0 V)
data input
data input
data input
data input
ground (0 V)
data input
data input
supply voltage
data input
data input
ground (0 V)
data input
data input
output enable input (active LOW)
2003 May 14
4
微控制器 MCU
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