74AUP2G00
Low-power dual 2-input NAND gate
Rev. 5 — 21 October 2010
Product data sheet
1. General description
The 74AUP2G00 provides dual 2-input NAND function.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1 000 V
Low static power consumption; I
CC
= 0.9
μA
(maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
−40 °C
to +85
°C
and
−40 °C
to +125
°C
NXP Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP2G00DC
74AUP2G00GT
74AUP2G00GF
74AUP2G00GD
74AUP2G00GM
74AUP2G00GN
74AUP2G00GS
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
VSSOP8
XSON8
XSON8
Description
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1
×
1.95
×
0.5 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
×
1
×
0.5 mm
Version
SOT765-1
SOT833-1
SOT1089
SOT996-2
SOT902-1
SOT1116
SOT1203
Type number
XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3
×
2
×
0.5 mm
XQFN8U plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6
×
1.6
×
0.5 mm
XSON8
XSON8
extremely thin small outline package; no leads;
8 terminals; body 1.2
×
1.0
×
0.35 mm
extremely thin small outline package; no leads;
8 terminals; body 1.35
×
1.0
×
0.35 mm
4. Marking
Table 2.
Marking codes
Marking code
[1]
p00
p00
pA
p00
p00
pA
pA
Type number
74AUP2G00DC
74AUP2G00GT
74AUP2G00GF
74AUP2G00GD
74AUP2G00GM
74AUP2G00GN
74AUP2G00GS
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
&
1A
1B
2A
2B
1Y
B
2Y
&
A
001aah749
Y
mna099
001aah748
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74AUP2G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 21 October 2010
2 of 21
NXP Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
6. Pinning information
6.1 Pinning
74AUP2G00
1A
1
8
V
CC
1B
2
7
1Y
74AUP2G00
2Y
1A
1B
2Y
GND
1
2
3
4
001aae362
3
6
2B
8
7
6
5
V
CC
1Y
2B
2A
GND
4
5
2A
001aae363
Transparent top view
Fig 4.
Pin configuration SOT765-1
Fig 5.
Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G00
terminal 1
index area
1Y
1
V
CC
8
74AUP2G00
1A
1B
2Y
GND
1
2
3
4
8
7
6
5
V
CC
7
1A
2B
1Y
2B
2A
2A
2
6
1B
3
4
5
2Y
GND
001aae364
001aai218
Transparent top view
Transparent top view
Fig 6.
Pin configuration SOT996-2
Fig 7.
Pin configuration SOT902-1
6.2 Pin description
Table 3.
Symbol
Pin description
Pin
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
1A, 2A
1B, 2B
GND
1Y, 2Y
V
CC
74AUP2G00
Description
SOT902-1
7, 3
6, 2
4
1, 5
8
All information provided in this document is subject to legal disclaimers.
1, 5
2, 6
4
7, 3
8
data input
data input
ground (0 V)
data output
supply voltage
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 21 October 2010
3 of 21
NXP Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
7. Functional description
Table 4.
Input
nA
L
L
H
H
[1]
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
−0.5
−50
−0.5
−50
[1]
Max
+4.6
-
+4.6
-
+4.6
±20
50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
°C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
−0.5
-
-
−50
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
°C
the value of P
tot
derates linearly at 8.0 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 118
°C
the value of P
tot
derates linearly at 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
V
CC
V
I
V
O
T
amb
Δt/ΔV
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
−40
-
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
°C
ns/V
74AUP2G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 21 October 2010
4 of 21
NXP Semiconductors
74AUP2G00
Low-power dual 2-input NAND gate
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
°C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
−20 μA;
V
CC
= 0.8 V to 3.6 V
I
O
=
−1.1
mA; V
CC
= 1.1 V
I
O
=
−1.7
mA; V
CC
= 1.4 V
I
O
=
−1.9
mA; V
CC
= 1.65 V
I
O
=
−2.3
mA; V
CC
= 2.3 V
I
O
=
−3.1
mA; V
CC
= 2.3 V
I
O
=
−2.7
mA; V
CC
= 3.0 V
I
O
=
−4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
μA;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
I
I
I
OFF
ΔI
OFF
I
CC
ΔI
CC
C
I
C
O
input leakage current
power-off leakage current
additional power-off
leakage current
supply current
additional supply current
input capacitance
output capacitance
V
I
= GND to 3.6 V; V
CC
= 0 V to 3.6 V
V
I
or V
O
= 0 V to 3.6 V; V
CC
= 0 V
V
I
or V
O
= 0 V to 3.6 V;
V
CC
= 0 V to 0.2 V
V
I
= GND or V
CC
; I
O
= 0 A;
V
CC
= 0.8 V to 3.6 V
V
I
= V
CC
−
0.6 V; I
O
= 0 A;
V
CC
= 3.3 V
V
CC
= 0 V to 3.6 V; V
I
= GND or V
CC
V
O
= GND; V
CC
= 0 V
[1]
Conditions
Min
Typ
Max
-
-
-
-
Unit
V
V
V
V
0.70
×
V
CC
-
0.65
×
V
CC
-
1.6
2.0
-
-
-
-
V
CC
−
0.1
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.8
1.7
0.30
×
V
CC
V
0.35
×
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.3
×
V
CC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.2
±0.2
0.5
40
-
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μA
μA
μA
μA
μA
pF
pF
0.75
×
V
CC
-
74AUP2G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 5 — 21 October 2010
5 of 21
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