Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
FEATURES
•
5 V tolerant inputs, for interfacing with 5 V logic
•
Supply voltage range from 1.2 to 3.6 V
•
CMOS low power consumption
•
Direct interface with TTL levels
•
Inputs accept voltage up to 5.5 V
•
Complies with JEDEC standard no. 8-1A
•
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•
Specified from
−40
to +85
°C
and
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
Σ(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
Σ(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
.
FUNCTION TABLE
See note 1.
INPUT
nA
L
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
nB
L
H
L
H
PARAMETER
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
V
CC
= 3.3 V; notes 1 and 2
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
DESCRIPTION
74LVC86A
The 74LVC86A is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC86A provides the 2-input EXCLUSIVE-OR
function.
TYPICAL
3.0
5.0
20
ns
pF
pF
UNIT
OUTPUT
nY
L
H
H
L
2004 Mar 04
2
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86A
handbook, halfpage
handbook, halfpage
1A
1
VCC
14
13
12
4B
4A
4Y
3B
3A
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
MNA785
14 VCC
13 4B
12 4A
1B
1Y
2A
2B
2Y
2
3
4
5
6
7
Top view
GND
8
3Y
86
11 4Y
10 3B
9
3A
GND
(1)
11
10
9
8 3Y
MNA977
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
handbook, halfpage
handbook, halfpage
1
2
=1
3
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
4
=1
6
2Y
6
5
3Y
8
9
10
=1
8
4Y
11
12
MNA787
=1
11
13
MNA786
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Mar 04
4
Philips Semiconductors
Product specification
Quad 2-input EXCLUSIVE-OR gate
74LVC86A
handbook, halfpage
A
Y
B
MNA788
Fig.5 Logic diagram (one gate).
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
O
T
amb
t
r
, t
f
PARAMETER
supply voltage
input voltage
output voltage
operating ambient temperature
input rise and fall times
in free air
V
CC
= 1.2 to 2.7 V
V
CC
= 2.7 to 3.6 V
CONDITIONS
for maximum speed performance
for low-voltage applications
MIN.
2.7
1.2
0
0
−40
0
0
MAX.
3.6
3.6
5.5
V
CC
+125
20
10
V
V
V
V
°C
ns/V
ns/V
UNIT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
, I
GND
T
stg
P
tot
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70
°C
the value of P
tot
derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60
°C
the value of P
tot
derates linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
°C
the value of P
tot
derates linearly with 4.5 mW/K.
2004 Mar 04
5
PARAMETER
supply voltage
input diode current
input voltage
output diode current
output voltage
output source or sink current
V
CC
or GND current
storage temperature
power dissipation
T
amb
=
−40
to +125
°C;
note 2
V
I
< 0
note 1
V
O
> V
CC
or V
O
< 0
note 1
V
O
= 0 to V
CC
CONDITIONS
−
−0.5
−
−0.5
−
−
−65
−
MIN.
−0.5
MAX.
+6.5
−50
+6.5
±50
V
CC
+ 0.5
±50
±100
+150
500
V
mA
V
mA
V
mA
mA
°C
mW
UNIT
PCB设计
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