HD66520T
(160-Channel 4-Level Grayscale Display Column Driver with
Internal Bit-Map RAM)
Description
The HD66520 is a column driver for liquid crystal dot-matrix graphic display systems. This LSI
incorporates 160 liquid crystal drive circuits and a 160
×
240
×
2-bit bit-map RAM, which is suitable for
LCDs in portable information devices. It also includes a general-purpose SRAM interface so that draw
access can be easily implemented from a general-purpose CPU. The HD66520 also has a new arbitration
method which prevents flicker when the CPU performs draw access asynchronously. The on-chip display
RAM greatly decreases power consumption compared to previous liquid crystal display systems because
there is no need for high-speed data transfer. The chip also incorporates a four-level grayscale controller
for enhanced graphics capabilities, such as icons on a screen.
Features
•
•
•
•
•
•
•
•
Duty cycle: 1/64 to 1/240
Liquid crystal drive circuits: 160
Low-voltage logic circuit: 3.0 to 5.5-V operation power supply voltage
High-voltage liquid crystal drive circuit: 8 to 28-V liquid crystal drive voltage
Grayscale display: FRC four-level grayscale display
Grayscale memory management: Packed pixel
Internal bit-map display RAM: 76800 bits (160
×
240 lines
×
two planes)
CPU interface
SRAM interface
Address bus: 16 bits, data bus: 8 bits
1014
HD66520T
•
High-speed draw function: Supports burst transfer mode
•
Arbitration function: Implemented internally (draw access has priority)
•
Access time
180 ns (V
CC
= 5V operation)
240 ns (V
CC
= 3V operation)
•
Low power consumption:
V
CC
= 3.3-V operation
360 µA during display (logic circuit, liquid crystal drive circuit)
10 mA during RAM access (logic circuit)
V
CC
= 5.5-V operation
400 µA during display (logic circuit, liquid crystal drive circuit)
16 mA during RAM access (logic circuit)
•
On-chip address management function
•
Refresh unnecessary
•
Internal display off function
•
Package: 208-pin TCP
Ordering Information
Type No.
HD66520TA0
HD66520TB0
TCP
Straight TCP
Folding TCP
Outer Lead Pitch (µm)
200
200
1015
1016
Note : This figure does not specify the TCP dimensions.
160
159
158
157
156
155
154
153
152
151
Y160
Y159
Y158
Y157
Y156
Y155
Y154
Y153
Y152
Y151
HD66520T
Pin Arrangement
Top View
V2L
V4L
V3L
V1L
V
EE1
V
CC1
LS0
LS1
SHL
GND1
FLM
M
CL1
DISPOFF
CS
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
GND2
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
V
CC2
V
EE2
V1R
V3R
V4R
V2R
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
10
9
8
7
6
5
4
3
2
1
Y10
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
HD66520T
Pin Description
Classi-
fication
Power
supply
Symbol
V
CC1
V
CC2
GND1
GND2
V
EE1
V
EE2
V1L,
V1R
V2L,
V2R
V3L,
V3R
V4L,
V4R
Control
LS0,
LS1
SHL
FLM
CL1
M
',632)
)
Pin No.
Pin Name
V
CC
V
CC
GND
GND
LCD drive
circuit power
supply
LCD select
high-level
voltage
LCD select
low-level
voltage
LCD deselect
high-level
voltage
LCD deselect
low- level
voltage
LSI ID select
switch pin0
and 1
I/O
—
—
—
—
—
—
Input
Number
of Pins Function
V
CC
–GND: logic power supply
V
CC
–V
EE
: LCD drive circuit power supply
2
Input
2
LCD drive level power supplies See
Figure 1.
The user should apply the same
potential to the L and R side.
Input
2
Input
2
Input
2
Pins for setting LSI ID no (refer to
signals
Pin Functions
for details).
Reverses the relationship between LCD
drive output pins Y and addresses.
First line select signal.
Clock signal to transfer the line data to
an LCD display driver block.
Switching signal to convert LCD drive
output to AC.
Control signal to fix LCD driver outputs
to LCD select high level. When low,
LCD drive outputs Y1 to Y160 are set to
V1, or LCD select high level. Display
can be turned off by setting a common
driver to V1.
Shift direction Input
control signal
First line
marker
Data transfer
clock
AC switching
signal
Display off
signal
Input
Input
Input
Input
1
1
1
1
1
1017
HD66520T
Classi-
fication
Bus
interface
Symbol
A0 to
A15
Pin No.
Pin Name
I/O
Number
of Pins Function
16
Upper 9 bits (A15–A7) are used for the
duty-directional addresses, and lower 7
bits (A6–A0) for the output-pin
directional addresses (refer to
Pin
Functions
for details).
Packed-pixel 2-bit/pixel display data
transfer (refer to
Pin Functions
for
details).
LSI select signal during draw access
(refer to
Pin Functions
for details).
Write-enable signal during draw access
(refer to
Pin Functions
for details).
Output-enable signal during draw
access (refer to
Pin Functions
for
details).
Each Y outputs one of the four voltage
levels V1, V2, V3, or V4, depending on
the combination of the M signal and
data levels
Address input Input
DB0 to
DB7
&6
Data input/
output
Chip select
signal
Write signal
Output
enable signal
LCD drive
output
I/O
8
Input
Input
Input
1
1
1
:(
2(
LCD
drive
output
Y1 to
Y160
Output 160
Note: The number of input outer leads: 48
V1
V3
V4
V2
Figure 1 LCD Drive Levels
1018
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