PRODUCT PREVIEW
80960JD
3.3 V EMBEDDED 32-BIT MICROPROCESSOR
• 3.3 V, 5 V Tolerant, Version of the 80960JD Processor
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Pin/Code Compatible with all 80960Jx
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3.3 V Supply Voltage
Processors
s
High-Performance Embedded Architecture
s
s
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— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
Two-Way Set Associative Instruction Cache
— 80960JD - 4 Kbyte
— Programmable Cache Locking
Mechanism
Direct Mapped Data Cache
— 80960JD - 2 Kbyte
— Write Through Operation
On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
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— 5 V Tolerant Inputs
— TTL Compatible Outputs
High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
High-Speed Interrupt Controller
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Two On-Chip Timers
— Independent 32-Bit Counting
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
Halt Mode for Low Power
Compatibility
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IEEE 1149.1 (JTAG) Boundary Scan
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Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
132
PIN 1
99
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A80960JD
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33
NG80960JD
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Figure 1.
80960JD Microprocessor
© INTEL CORPORATION, 1996
November 1996
Order Number:
272971-001
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
*Third-party brands and names are the property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature, may be obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect IL 60056-764
or call 1-800-548-4725
©INTEL CORPORATION, 1996
Contents
80960JD
3.3 V EMBEDDED 32-BIT MICROPROCESSOR
1.0 PURPOSE .................................................................................................................................................. 1
2.0 80960JD OVERVIEW ................................................................................................................................ 1
2.1 80960 Processor Core ........................................................................................................................ 2
2.2 Burst Bus ............................................................................................................................................ 2
2.3 Timer Unit ........................................................................................................................................... 3
2.4 Priority Interrupt Controller ................................................................................................................. 3
2.5 Instruction Set Summary .................................................................................................................... 3
2.6 Faults and Debugging ........................................................................................................................ 3
2.7 Low Power Operation ......................................................................................................................... 3
2.8 Test Features ..................................................................................................................................... 4
2.9 Memory-Mapped Control Registers .................................................................................................... 4
2.10 Data Types and Memory Addressing Modes ................................................................................... 4
3.0 PACKAGE INFORMATION ....................................................................................................................... 6
3.1 Pin Descriptions .................................................................................................................................. 6
3.1.1 Functional Pin Definitions ........................................................................................................ 6
3.1.2 80960Jx 132-Lead PGA Pinout ............................................................................................. 12
3.1.3 80960Jx PQFP Pinout ........................................................................................................... 16
3.2 Package Thermal Specifications ...................................................................................................... 19
3.3 Thermal Management Accessories .................................................................................................. 21
4.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 22
4.1 Absolute Maximum Ratings .............................................................................................................. 22
4.2 Operating Conditions ........................................................................................................................ 22
4.3 Connection Recommendations ........................................................................................................ 22
4.4
V
CC5
Pin Requirements (V
DIFF
) ........................................................................................................ 23
4.5 VCCPLL Pin Requirements .............................................................................................................. 23
4.6 DC Specifications ............................................................................................................................. 24
4.7 AC Specifications ............................................................................................................................. 26
4.7.1 AC Test Conditions and Derating Curves .............................................................................. 29
4.7.2 AC Timing Waveforms ........................................................................................................... 30
5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 37
6.0 DEVICE IDENTIFICATION ...................................................................................................................... 51
7.0 REVISION HISTORY ............................................................................................................................... 53
iii
Contents
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
80960JD Microprocessor ................................................................................................................ i
80960JD Block Diagram ................................................................................................................ 2
132-Lead Pin Grid Array Bottom View - Pins Facing Up ............................................................. 12
132-Lead Pin Grid Array Top View - Pins Facing Down .............................................................. 13
132-Lead PQFP - Top View ......................................................................................................... 16
VCC5 Current-Limiting Resistor ................................................................................................... 23
VCCPLL Lowpass Filter ............................................................................................................... 23
AC Test Load ............................................................................................................................... 29
Output Delay or Hold vs. Load Capacitance ................................................................................ 29
CLKIN Waveform ......................................................................................................................... 30
Output Delay Waveform for T
OV1
................................................................................................ 30
Output Float Waveform for T
OF
................................................................................................... 31
Input Setup and Hold Waveform for T
IS1
and T
IH1
...................................................................... 31
Input Setup and Hold Waveform for T
IS2
and T
IH2
...................................................................... 32
Input Setup and Hold Waveform for T
IS3
and T
IH3
...................................................................... 32
Input Setup and Hold Waveform for T
IS4
and T
IH4
...................................................................... 33
Relative Timings Waveform for T
LX
, T
LXL
and T
LXA
.................................................................... 33
DT/R and DEN Timings Waveform .............................................................................................. 34
TCK Waveform ............................................................................................................................ 34
Input Setup and Hold Waveforms for T
BSIS1
and T
BSIH1
............................................................. 35
Output Delay and Output Float Waveform for T
BSOV1
AND T
BSOF1
............................................ 35
Output Delay and Output Float Waveform for T
BSOV2
and T
BSOF2
............................................. 36
Input Setup and Hold Waveform for T
BSIS2
and T
BSIH2
............................................................... 36
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .................................. 37
Burst Read and Write Transactions Without Wait States, 32-Bit Bus .......................................... 38
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................... 39
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ............................................ 40
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ....................................................................................... 41
Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian .............................. 42
HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 43
Cold Reset Waveform .................................................................................................................. 44
Warm Reset Waveform ................................................................................................................ 45
Entering the ONCE State ............................................................................................................. 46
Summary of Aligned and Unaligned Accesses (32-Bit Bus) ........................................................ 49
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) .................................... 50
80960JD Device Identification Register ....................................................................................... 51
iv
Contents
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
80960Jx Instruction Set ................................................................................................................. 5
Pin Description Nomenclature ....................................................................................................... 6
Pin Description — External Bus Signals ........................................................................................ 7
Pin Description — Processor Control Signals, Test Signals and Power ..................................... 10
Pin Description — Interrupt Unit Signals ..................................................................................... 11
132-Lead PGA Pinout — In Signal Order .................................................................................... 14
132-Lead PGA Pinout — In Pin Order ......................................................................................... 15
132-Lead PQFP Pinout — In Signal Order .................................................................................. 17
132-Lead PQFP Pinout — In Pin Order ....................................................................................... 18
132-Lead PGA Package Thermal Characteristics ....................................................................... 19
132-Lead PQFP Package Thermal Characteristics ..................................................................... 20
Maximum T
A
at Various Airflows in °C ......................................................................................... 21
80960JD Operating Conditions .................................................................................................... 22
80960JD DC Characteristics ....................................................................................................... 24
80960JD ICC Characteristics ...................................................................................................... 25
80960JD AC Characteristics ........................................................................................................ 26
Note Definitions for Table 16, 80960JD AC Characteristics (pg. 26) ........................................... 28
Natural Boundaries for Load and Store Accesses ....................................................................... 47
Summary of Byte Load and Store Accesses ............................................................................... 47
Summary of Short Word Load and Store Accesses .................................................................... 47
Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ................................................... 48
80960JD66 Die and Stepping Reference .................................................................................... 51
Fields of 80960JD Device ID ....................................................................................................... 52
80960JD Device ID Model Types ................................................................................................ 52
Device ID Version Numbers for Different Steppings .................................................................... 52
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