PACUSBVB-D1/D2/D3
USB Downstream Port Terminator with
VBUS ESD Protection
Features
•
•
•
•
•
•
•
A low-capacitance USB downstream port termina-
tor, EMI filter, and transient over-voltage protector
in a single surface-mounted package
ESD protection to
±20kV
contact discharge, per
MIL-STD-883D, Method 3015
ESD protection to
±15kV
contact discharge, per
IEC 61000-4-2 International Standard
Provides ESD protection for the VBUS line
Compact SOT23-6 package saves board space
and lowers manufacturing costs compared to dis-
crete solutions
Capacitors matched to a precision exceeding the
USB specification
Lead-free versions available
Product Description
The PACUSBVB-D1/D2/D3 is a single-channel USB
downstream-port termination network. It integrates
EMI/RFI filter components R1 and C1 as recom-
mended by the USB specification, as well as the
required 15kΩ pull-down resistors (R2) to GND. In
addition, PACUSBVB-D1/D2/D3 provides a very high
level of protection for sensitive electronic components
that may be subjected to electrostatic discharge (ESD).
The device pins will safely dissipate ESD strikes of
±15kV,
exceeding the maximum requirements of the
IEC 61000-4-2 international standard. Using the MIL-
STD-883D (Method 3015) specification for Human
Body Model (HBM) ESD, all pins are protected from
contact discharges to
±20kV.
The PACUSBVB-D1/D2/D3 also features a fifth zener
diode (cathode at pin 5) which provides ESD protection
for the USB VBUS line.
There are three options for the value of the series
resistor R1: 15Ω, 33Ω, and 22Ω. This series resis-
tance, plus the USB driver output resistance, must be
close to the USB cable’s characteristic impedance of
45Ω (each side) to minimize transmission line reflec-
tions.
The PACUSBVB-D1/D2/D3 is housed in a 6-pin
SOT23 package and is available with optional lead-
free finishing.
Applications
•
•
•
•
•
ESD protection and termination of USB
downstream ports
Desktop PCs
Notebooks
Set-top boxes
USB hubs
Electrical Schematic
1
C1
2
GND
C1
3
R1
R2
6
R2
R1
5
V
BUS
4
©
2004 California Micro Devices Corp. All rights reserved.
11/15/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
1
PACUSBVB-D1/D2/D3
PACKAGE / PINOUT DIAGRAMS
Top View
D+ CNTR
GND
D- CNTR
1
6
D+ CONN
V
BUS
D- CONN
UDn /
UDnR
2
5
3
4
6-pin SOT23
Note 1: The "n" shown in part markings above represents either the digit "1," "2," or "3."
Note 2: These drawings are not to scale.
PIN DESCRIPTIONS
PINS
1
2
3
4
5
6
NAME
D+ CNTR
GND
D- CNTR
D- CONN
V
BUS
D+ CONN
DESCRIPTION
D+ Data to the USB controller circuitry
Ground Pin
D- Data to the USB controller circuitry
D- Data to the USB connector
V
BUS
input pin
D+ Data to the USB connector
Ordering Information
PART NUMBERING INFORMATION
Standard Finish
Pins
6
R1 Value
15
Ω
22
Ω
33
Ω
Package
SOT23-6
Ordering Part
Number
1
PACUSBVB-D2Y6
PACUSBVB-D3Y6
PACUSBVB-D1Y6
Part Marking
UD2
UD3
UD1
Lead-free Finish
Ordering Part
Number
1
PACUSBVB-D2Y6R
PACUSBVB-D3Y6R
PACUSBVB-D1Y6R
Part Marking
UD2R
UD3R
UD1R
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
©
2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
11/15/04
PACUSBVB-D1/D2/D3
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Storage Temperature Range
Power Dissipation per Resistor
Package Power Dissipation
Voltage on any pin (DC)
RATING
-65 to +150
100
200
6
UNITS
°C
mW
mW
V
STANDARD OPERATING CONDITIONS
PARAMETER
Operating Temperature
V
BUS
Input Voltage
RATING
-40 to +85
5
UNITS
°C
V
©
2004 California Micro Devices Corp. All rights reserved.
11/15/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
3
PACUSBVB-D1/D2/D3
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
SYMBOL
R1
R1
R1
R2
TCR
C1
TOL
CM
I
LEAK
V
RB
V
SIG
PARAMETER
Resistance of R1 Resistor
(PACUSBVB-D2Y6/Y6R)
Resistance of R1 Resistor
(PACUSBVB-D3Y6/Y6R)
Resistance of R1 Resistor
(PACUSBVB-D1Y6/Y6R)
Resistance of R2 Resistor
Temperature Coefficient of Resis-
tance
Capacitance of C1 Capacitor
CONDITIONS
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
Note 1
0 VDC; 30 mVAC; 1MHz; 25°C
2.5 VDC; 30 mVAC; 1MHz; 25°C
Matching Tolerance of C1 Capacitors 1MHz; 25°C
Diode Leakage Current to GND
Diode Reverse Bias Voltage
Signal Voltage:
Positive Clamp
Negative Clamp
In-system ESD Withstand Voltage
MIL-STD-883D, Method 3015
(HBM)
IEC 61000-4-2 Contact Dis-
charge
V
CL
Clamping voltage under ESD
discharge
Pins 1, 3; Notes 1, 2 and 3
Pins 4, 5; Notes 1 and 2
Pins 4, 5; Notes 1 and 2
MIL-STD-883D, Method 3015 +8kV;
Notes 1 and 4
MIL-STD-883D, Method 3015 -8kV;
Notes 1 and 4
Measured at 3.3 VDC, 25°C
I
LOAD
= 10μA; T
A
= 25°C
I
LOAD
= 10mA; T
A
= 25°C
I
LOAD
= 10mA; T
A
= 25°C
5.5
5.6
-0.4
6.8
-0.8
9.0
-1.5
1
37.6
25.6
MIN
12
17.6
26.4
TYP
15
22
33
15
+1300
47
32
56.4
38.4
+2
100
MAX
18
26.4
39.6
UNITS
Ω
Ω
Ω
kΩ
ppm/
°C
pF
pF
%
nA
V
V
V
kV
kV
kV
12
-7
V
V
V
ESD
±
4
±
20
±
15
Note 1: Guaranteed by design and characterization.
Note 2: ESD voltage applied to pins with respect to GND, one at a time; unused pins are left open.
Note 3: Pins 1 and 3 are not connected to the USB port connector, and therefore are not exposed to external ESD hazards. Thus,
they do not require the high ESD protection levels provided for pins 4, 5, and 6.
Note 4: ESD Clamping Voltage is measured at the opposite end of R1 from the pin to which the ESD discharge is applied (e.g., if
ESD is applied to pin 6, then the clamping voltage is measured at pin 1).
©
2004 California Micro Devices Corp. All rights reserved.
4
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
11/15/04
PACUSBVB-D1/D2/D3
Performance Information
Capacitance vs. Voltage
The C1 capacitance value as a function of DC voltage
across it is presented in
Figure 1.
The curve is normal-
ized to a capacitance of 1.0 capacitance units at 2.5
VDC.
1.6
1.4
Normalized C1 Capacitance
1.2
1.0
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
DC Voltage
Figure 1. Diode Capacitance vs. DC Voltage (Normalized)
Insertion Loss vs. Frequency Characteristics
Figure 2. Insertion Loss vs. Frequency Performance Curve, PACUSBVB-D1 (SOT23-6)
©
2004 California Micro Devices Corp. All rights reserved.
11/15/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
●
Fax: 408.263.7846
●
www.calmicro.com
5
/pacusbvb_d2y6r_pdf/pg_0001.png)
ST传感器与低功耗无线技术论坛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界/pacusbvb_d2y6r_pdf/1.png)
/pacusbvb_d2y6r_pdf/2.png)
/pacusbvb_d2y6r_pdf/3.png)
/pacusbvb_d2y6r_pdf/4.png)
/pacusbvb_d2y6r_pdf/5.png)
/pacusbvb_d2y6r_pdf/pg_0002.png)
/pacusbvb_d2y6r_pdf/pg_0003.png)
/pacusbvb_d2y6r_pdf/pg_0004.png)
/pacusbvb_d2y6r_pdf/pg_0005.png)
