......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-65°C to +125°C
ESD protection on all pins ......................................................................................................................................
≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= +4.5V to +5.5V
Commercial (C): T
A
= 0°C to +70°C
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E):
T
A
= -40°C to +125°C
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
Read
I
CC
Write
I
CCS
Min.
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
—
Max.
—
0.3 V
CC
—
0.40
±1
±1
10
1
3
50
Units
V
V
V
V
µA
µA
pF
mA
mA
µA
(Note)
I
OL
= 3.0 mA, Vcc = 4.5V
V
IN
= 0.1V to 5.5V, WP = Vss
V
OUT
= 0.1V to 5.5V
V
CC
= 5.0V
(Note)
T
A
= 25°C, f = 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
V
CC
= 5.5V, SDA = SCL = V
CC
WP = V
SS
Conditions
All parameters apply across the
specified operating ranges unless
otherwise noted.
Parameter
SCL and SDA pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note:
This parameter is periodically sampled and not 100% tested.
DS21202D-page 2
2003 Microchip Technology Inc.
24C02C
TABLE 1-2:
AC CHARACTERISTICS
V
CC
= +4.5V to +5.5V
Commercial (C): T
A
= 0°C to +70°C
Industrial (I):
T
A
= -40°C to +85°C
Automotive (E):
T
A
= -40°C to +125°C
T
A
>
+85°C
Min.
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
-40°C
≤
T
A
≤
+85°C
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Remarks
All parameters apply across the
specified operating ranges unless
otherwise noted.
Parameter
Symbol
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
Start condition
(Note 2)
T
OF
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression T
SP
(SDA and SCL pins)
Write cycle time
T
WR
Endurance
Note 1:
2:
3:
4:
—
—
—
1M
250
50
1.5
—
20 + 0.1 C
B
—
—
1M
250
50
1
—
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1),
C
B
≤
100 pF
(Note 3)
ms Byte or Page mode
cycles 25°C, V
CC
= 5.0V, Block
mode
(Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
FIGURE 1-1:
BUS TIMING DATA
T
F
T
HIGH
T
R
SCL
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
SP
T
HD
:
STA
T
AA
SDA
OUT
T
BUF
2003 Microchip Technology Inc.
DS21202D-page 3
24C02C
2.0
PIN DESCRIPTIONS
3.0
FUNCTIONAL DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
The 24C02C supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the Start
and Stop conditions, while the 24C02C works as slave.
Both master and slave can operate as transmitter or
receiver but the master device determines which mode
is activated.
TABLE 2-1:
Name
Vss
SDA
SCL
V
CC
A0, A1, A2
WP
PIN FUNCTION TABLE
Function
Ground
Serial Data
Serial Clock
+4.5V to 5.5V Power Supply
Chip Selects
Hardware Write-Protect
2.1
SDA Serial Data
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.3
A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24C02C devices may be connected to the
same bus by using different Chip Select bit combina-
tions. These inputs must be connected to either V
CC
or
V
SS
.
2.4
WP
This is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, the hardware write protection
is enabled. If the WP pin is tied to Vss the hardware
write protection is disabled.
2.5
Noise Protection
The 24C02C employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 3.8 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
DS21202D-page 4
2003 Microchip Technology Inc.
24C02C
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
4.1
Bus not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24C02C does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All opera-
tions must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 4-2).
FIGURE 4-1:
SCL
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C)
(D)
(C)
(A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Transmitter must release the SDA line at this point
Arm 助力车厂将新车型上市时间至少提前一年。 Zena CSS 加速了软件和芯片开发进程，助力更快速、高效地交付 AI 功能。 作为预先验证且具备安全能力的计算平台，Zena CSS 能够节省约 20% 的工程资源，大幅降低开发的成本和复杂性。 未来几年，大多数汽车制造商将会基于 Zena CSS 产品系列进行开发 Arm 控股有限公司 近期宣布推出 Arm® Zena 计...[详细]
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
