1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
SMALL-OUTLINE
DDR SDRAM DIMM
Features
• 200-pin, small-outline, dual in-line memory
module (SODIMM)
• Supports ECC error detection and correction
• Fast data transfer rate: PC2100 and PC2700
• Utilizes 267 MT/s and 333 MT/s DDR SDRAM
components
• 1GB (128 Meg x 72, stacked)
• V
DD
= V
DD
Q = +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/re-
ceived with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
MT18VDDT12872PH(I) – 1GB
For the lastest data sheet, please refer to the Micron
Web site:
www.micron.com/module.
Figure 1: 200-Pin SODIMM (MO-224)
Height 1.25in. (31.75mm)
OPTIONS
MARKING
• Operating Temperature Range
Commercial (0°C
≤
T
A
≤
+70°C)
Industrial (-40°C
≤
T
A
≤
+85°C)
• Package
200-pin SODIMM (standard)
200-pin SODIMM (lead-free)
• Clock Frequency/CAS Latency
167 MHz (333 MT/s) CL = 2.5
1
133 MHz (266 MT/s) CL = 2
1
133 MHz (266 MT/s) CL = 2
1
133 MHz (266 MT/s) CL = 2.5
1
• PCB Height
Standard 1.25in. (31.75mm)
NOTE:
None
I
2
G
Y
-335
-262
-26A
-265
1. CL = Device CAS (READ) Latency.
2. Consult Micron for product availability.
Table 1:
Address Table
1GB
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
2 (S0#, S1#)
Refresh Count
Row Addressing
Device Bank Addressing
Base Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
CONFIGURATION
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
MODULE
BANDWIDTH
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
MEMORY CLOCK/
DATA RATE
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
CLOCK LATENCY
(CL -
t
RCD -
t
RP)
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2.5-3-3
PART NUMBER
MT18VDDT12872PHG-335__
MT18VDDT12872PHY-335__
MT18VDDT12872PHG-262__
MT18VDDT12872PHY-262__
MT18VDDT12872PHG-26A__
MT18VDDT12872PHY-26A__
MT18VDDT12872PHG-265__
MT18VDDT12872PHY-265__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT18VDDT12872PHG-335A1.
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
Table 3:
Pin Assignment
(200-Pin SODIMM Front)
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
V
SS
DQ19
DQ24
V
DD
DQ25
DQS3
V
SS
DQ26
DQ27
V
DD
CB0
CB1
V
SS
DQS8
CB2
V
DD
CB3
NC
V
SS
NC
NC
V
DD
CKE1
NC
A12
101
A9
151 DQ42
103
V
SS
153 DQ43
105
A7
155
V
DD
107
A5
157
V
DD
109
A3
159
V
SS
111
A1
161
V
SS
113
V
DD
163 DQ48
115 A10/AP
165 DQ49
117
BA0
167
V
DD
119
WE#
169 DQS6
121
S0#
171 DQ50
123
NC
173
V
SS
125
V
SS
175 DQ51
127 DQ32 177 DQ56
129 DQ33
179
V
DD
131
V
DD
181 DQ57
133 DQS4 183 DQS7
135 DQ34
185
V
SS
137
V
SS
187 DQ58
139 DQ35 189 DQ59
141 DQ40
191
V
DD
143
V
DD
193
SDA
145 DQ41
195
SCL
147 DQS5 197 V
DDSPD
149
V
SS
199
NC
Table 4:
Pin Assignment
(200-Pin SODIMM Back)
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
V
SS
DQ23
DQ28
V
DD
DQ29
DM3
V
SS
DQ30
DQ31
V
DD
CB4
CB5
V
SS
DM8
CB6
V
DD
CB7
NC
V
SS
V
SS
V
DD
V
DD
CKE0
NC
A11
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
A8
V
SS
A6
A4
A2
A0
V
DD
BA1
RAS#
CAS#
S1#
NC
V
SS
DQ36
DQ37
V
DD
DM4
DQ38
V
SS
DQ39
DQ44
V
DD
DQ45
DM5
V
SS
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ46
DQ47
V
DD
NC
NC
V
SS
DQ52
DQ53
V
DD
DM6
DQ54
V
SS
DQ55
DQ60
V
DD
DQ61
DM7
V
SS
DQ62
DQ63
V
DD
SA0
SA1
SA2
NC
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
V
REF
V
SS
DQ0
DQ1
Vdd
DQS0
DQ2
V
SS
DQ3
DQ8
V
DD
DQ9
DQS1
V
SS
DQ10
DQ11
V
DD
CK0
CK0#
V
SS
DQ16
DQ17
V
DD
DQS2
DQ18
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
V
REF
V
SS
DQ4
DQ5
V
DD
DM0
DQ6
V
SS
DQ7
DQ12
V
DD
DQ13
DM1
V
SS
DQ14
DQ15
V
DD
V
DD
V
SS
V
SS
DQ20
DQ21
V
DD
DM2
DQ22
Figure 2: Module Layout
Front View
Back View
U8
U1
U2
U3
U4
U5
U6
U7
U10
U11
U9
PIN 1
(all odd pins)
PIN 199
PIN 200
(all even pins)
PIN 2
Indicates a V
DD
or V
DD
Q pin
Indicates a V
SS
pin
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK and CK# are differential clock inputs distributed
through an on-board PLL to all devices. All address and control
input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQ and DQS) is
referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers.and output drivers. Taking CKE
LOW provides PRECHARGE POWER- DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. Input buffers (excluding CKE)
are disabled during SELF REFRESH. CKE is an SSTL_2 input but
will detect an LVCMOS LOW level after V
DD
is applied and until
CKE is first brought HIGH. After CKE is brought HIGH, it
becomes an SSTL_2 input only.
Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All com- mands are
masked when S# is registered HIGH. S# is considered part of the
command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: A0–A12 provide the row address for ACTIVE
commands, and the column address, and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of
the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0, BA1) or all device banks (A10 HIGH). The
address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Mask: DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.
Check Bits.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
118, 119, 120
35, 37
95, 96
CKE0, CKE1
Input
121, 122
S0#, S1#
Input
117, 116
BA0, BA1
Input
99, 100, 101,102, 105,
106, 107, 108, 109, 110,
111, 112, 115
A0–A12
Input
11, 25, 47, 61, 77, 133,
147,169, 183
12, 26, 48, 62, 78, 134,
148, 170, 184
DQS0–DQS8
Input/
Output
Input
DM0–DM8
71, 72, 73, 74, 79, 80, 83,
84
CB0–CB7
Input/
Output
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1GB (x72, ECC, PLL)
200-PIN DDR SDRAM SODIMM
Table 5:
Pin Descriptions
SYMBOL
DQ0–DQ63
TYPE
Input/
Output
Data I/Os: Data bus.
DESCRIPTION
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
5, 6, 7, 8, 13, 14, 17, 18,
19, 20, 23, 24, 29, 30, 31,
32, 41, 42, 43, 44, 49, 50,
53, 54, 55, 56, 59, 60, 61,
65, 66, 67, 68, 127, 128,
129, 130, 135, 136, 139,
140, 141, 142, 145, 146,
151, 152, 153, 154, 163,
164, 165, 166, 171, 172,
175, 176, 177, 181, 182,
187, 188, 189, 190
195
194, 196, 198
193
SCL
SA0–SA2
SDA
Input
Input
Input/
Output
Supply
Supply
1, 2
9, 10, 21, 22, 33, 34, 36,
45, 46, 57, 58, 69, 70, 81,
82, 92, 93, 94, 113, 114,
131, 132, 143, 144, 155,
156, 157, 167, 168, 179,
180, 191, 192
3, 4, 15, 16, 27, 28, 38,
39, 40, 51, 52, 63, 64, 75,
76, 87, 88, 90, 103, 104,
125, 126, 137, 138, 149,
150, 159, 161, 162, 173,
174, 185, 186
197
85, 86, 89, 91, 97, 98
,
123
,
124, 158, 160, 200
V
REF
V
DD
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
SSTL_2 reference voltage.
DQ Power Supply: +2.5V ±0.2V.
V
SS
Supply
Ground.
V
DDSPD
NC
Supply
–
Serial EEPROM positive power supply: +2.3V to +3.6V.
No Connect: These pins should be left unconnected.
pdf: 09005aef81697898/source: 09005aef8169786e
DD18C128x72PHG.fm - Rev. A 10/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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