CD40104BMS,
CD40194BMS
December 1992
CMOS 4-Bit Bidirectional
Universal Shift Register
Pinouts
OUTPUT ENABLE 1
SHIFT RIGHT IN 2
D0 3
D1 4
D2 5
D3 6
SHIFT LEVEL IN 7
VSS 8
Features
• High Voltage Type (20V Rating)
• Medium Speed fCL = 12MHz (typ.) at VDD = 10V
• Fully Static Operation
• Synchronous Parallel or Serial Operation
• Three State Outputs (CD40104BMS)
• Asynchronous Master Reset (CD40194BMS)
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD40104BMS
TOP VIEW
16 VDD
15 Q0
14 Q1
13 Q2
12 Q3
11 CLOCK
10 SELECT 1
9 SELECT 0
Applications
• Arithmetic Unit Bus Registers
• Serial/Parallel Conversions
• General Purpose Register for Bus Organized Systems
• General Purpose Registers
RESET 1
SHIFT RIGHT IN 2
D0 3
D1 4
D2 5
D3 6
SHIFT LEVEL IN 7
VSS 8
CD40194BMS
TOP VIEW
16 VDD
15 Q0
14 Q1
13 Q2
12 Q3
11 CLOCK
10 SELECT 1
9 SELECT 0
Description
The CD40104BMS is a universal shift register featuring parallel
inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial
inputs, and a high impedance third output state allowing the device
to be used in bus organized systems.
In the parallel load mode (S0 and S1 are high), data is loaded into
the associated flip-flop and appears at the output after the positive
transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right and shift left are accomplished synchronously
on the positive clock edge with serial data entered at the SHIFT
RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the
register is accomplished by setting both mode controls low and
clocking the register. When the output enable input is low, all outputs
assume the high impedance state.
The CD40194BMS is a universal shift register featuring parallel inputs,
parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a
direct overriding clear input. In the parallel load mode (S0 and S1 are
high), data is loaded into the associated flip-flop and appears at the out-
put after the positive transition of the CLOCK input. During loading,
serial data flow is inhibited. Shift right and shift left are accomplished
synchronously on the positive clock edge with data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of
the register is inhibited when both mode control inputs are low. When
low, the RESET input resets all stages and forces all outputs low. The
CD40194BMS is similar to industry types 340194 and MC40194.
The CD40104BMS and CD40194BMS series types are supplied in
these 16 lead outline packages
Functional Diagrams
CD40104BMS
OUTPUT ENABLE
D0
D1
D2
D3
SHIFT LEFT IN
SHIFT RIGHT IN
S0
MODE SELECT
S1
CLOCK
3
4
5
6
7
2
9
10
11
1
15
Q0
14
Q1
13
Q2
12
Q3
VDD = 16
VSS = 8
CD40194BMS
RESET
D0
D1
D2
D3
SHIFT LEFT IN
SHIFT RIGHT IN
S0
MODE SELECT
S1
CLOCK
3
4
5
6
7
2
9
10
11
1
15
Q0
14
Q1
13
Q2
12
Q3
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
* CD40104B Only
*HNX,
*H1L,
H6W
†H4W
†HIF
VDD = 16
VSS = 8
†CD40194B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3352
7-1307
Specifications CD40104BMS, CD40194BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input
. . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65
o
C to +150
o
C
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265
o
C
At Distance 1/16
±
1/32 Inch (1.59mm
±
0.79mm) from case for
10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
θ
ja
θ
jc
o
C/W
o
C/W
Ceramic DIP and FRIT Package . . . . . 80
20
Flatpack Package . . . . . . . . . . . . . . . . 70
o
C/W
20
o
C/W
Maximum Package Power Dissipation (PD) at +125
o
C
For T
A
= -55
o
C to +100
o
C (Package Type D, F, K) . . . . . . 500mW
For T
A
= +100
o
C to +125
o
C (Package Type D, F, K). . . . . . Derate
Linearity at 12mW/
o
C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For T
A
= Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS
1
2
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20V
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20V
VDD = 18V
Output Voltage
Output Voltage
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
N Threshold Voltage
P Threshold Voltage
Functional
VOL15
VOH15
IOL5
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VNTH
VPTH
F
VDD = 15V, No Load
VDD = 15V, No Load (Note 3)
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
VDD = 10V, VOUT = 9.5V
VDD = 15V, VOUT = 13.5V
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Input Voltage Low
(Note 2)
Input Voltage High
(Note 2)
Tri-State Output
Leakage
VIL
VIH
VIL
VIH
IOZL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 5V, VOH > 4.5V, VOL < 0.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
VIN = VDD or GND
VOUT = 0V
VDD = 20V
VDD = 18V
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
VDD = 20V
VDD = 18V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3
1
2
3
1
2
3
1, 2, 3
1, 2, 3
1
1
1
1
1
1
1
1
1
7
7
8A
8B
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1
2
3
1
2
3
+25
o
C,
LIMITS
TEMPERATURE
+25
o
C
+125 C
-55
o
C
+25
o
C
+125 C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+125
o
C,
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C, +125
o
C, -55
o
C
+25
o
C
+125
o
C
-55
o
C
+25
o
C
+125
o
C
-55
o
C
-
3.5
-
11
-0.4
-12
-0.4
-
-
-
1.5
-
4
-
-
-
-
0.4
12
0.4
V
V
V
V
µA
µA
µA
µA
µA
µA
-55
o
C
o
o
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
(NOTE 1)
VDD = 20V, VIN = VDD or GND
MIN
-
-
-
-100
-1000
-100
-
-
-
-
14.95
0.53
1.4
3.5
-
-
-
-
-2.8
0.7
MAX
10
1000
10
-
-
-
100
1000
100
50
-
-
-
-
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
UNITS
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
mA
mA
mA
mA
mA
mA
mA
V
V
V
VOH > VOL <
VDD/2 VDD/2
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-1308
Specifications CD40104BMS, CD40194BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
9
10, 11
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
+25
o
C
+125
o
C, -55
o
C
LIMITS
MIN
-
-
-
-
-
-
-
-
-
-
3
2.22
MAX
440
594
460
621
160
216
90
122
200
270
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
PARAMETER
Propagation Delay
Clock to Q
Propagation Delay
CD40194BMS Reset to Q
Propagation Delay
CD40104BMS 3-State
Propagation Delay
CD40104BMS 3-State
Transition Time
SYMBOL
TPHL
TPLH
TPHL
CONDITIONS
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
VDD = 5V, VIN = VDD or GND
(Note 2, 3)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
VDD = 5V, VIN = VDD or GND
(Note 1, 2)
TPZH
TPZL
TPLZ
TPHZ
TTHL
TTLH
FCL
Maximum Clock Input
Frequency
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55
o
C and +125
o
C limits guaranteed, 100% testing being implemented.
3. VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
VDD = 5V, VIN = VDD or GND
NOTES
1, 2
TEMPERATURE
-55
o
C, +25
o
C
+125
o
C
VDD = 10V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
VDD = 15V, VIN = VDD or GND
1, 2
-55
o
C, +25
o
C
+125
o
C
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+125
o
C
-55
o
C
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1, 2
+125
o
C
-55
o
C
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH5A
VDD = 5V, VOUT = 4.6V
1, 2
+125
o
C
-55
o
C
MIN
-
-
-
-
-
-
-
-
4.95
9.95
0.36
0.64
0.9
1.6
2.4
4.2
-
-
MAX
5
150
10
300
10
600
50
50
-
-
-
-
-
-
-
-
-0.36
-0.64
UNITS
µA
µA
µA
µA
µA
µA
mV
mV
V
V
mA
mA
mA
mA
mA
mA
mA
mA
7-1309
Specifications CD40104BMS, CD40194BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Output Current (Source)
SYMBOL
IOH5B
CONDITIONS
VDD = 5V, VOUT = 2.5V
NOTES
1, 2
TEMPERATURE
+125
o
C
-55
o
C
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1, 2
+125
o
C
-55
o
C
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125
o
C
-55
o
C
Input Voltage Low
Input Voltage High
Propagation Delay
Clock to Q
Propagation Delay
CD40194B Reset to Q
Propagation Delay
CD40104BMS 3-State
Propagation Delay
CD40104BMS 3-State
Transition Time
VIL
VIH
TPHL
TPLH
TPLH
TPHL
TPZH
TPZL
TPLZ
TPHZ
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V, VOH > 9V,
VOL < 1V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
TTHL
TTLH
TS
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Data Hold Time
D0, D3, SRIN, SLIN to
Clock
Minimum Clock Pulse
Width
TH
VDD = 5V
VDD = 10V
VDD = 15V
TW
VDD = 5V
VDD = 10V
VDD = 15V
Maximum Clock Rise and
Fall Time
TRCL
TFCL
VDD = 5V
VDD = 10V
VDD = 15V
Minimum Data Setup
Time
Select 1, Select 0 to
Clock
Minimum Data Hold Time
Select 1, Select 0 to
Clock
TS
VDD = 5V
VDD = 10V
VDD = 15V
TH
VDD = 5V
VDD = 10V
VDD = 15V
1, 2
1, 2
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 4
1, 2, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3, 5
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
+25
o
C, +125
o
C,
-55
o
C
+25
o
C, +125
o
C,
-55
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
6
8
-
-
-
-
-
-
MAX
-1.15
-2.0
-0.9
-1.6
-2.4
-4.2
3
-
200
140
180
130
70
50
50
40
100
80
100
70
50
0
0
0
180
80
50
-
-
-
400
220
130
0
0
0
UNITS
mA
mA
mA
mA
mA
mA
V
V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
Minimum Data Setup
Time, D0, D3, SRIN,
SLIN to Clock
7-1310
Specifications CD40104BMS, CD40194BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
(Continued)
LIMITS
PARAMETER
Minimum Reset Pulse
Width CD40194BMS
SYMBOL
TW
CONDITIONS
VDD = 5V
VDD = 10V
VDD = 15V
Input Capacitance
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
CIN
Any Input
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-
-
-
MAX
300
200
140
7.5
UNITS
ns
ns
ns
pF
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
SYMBOL
IDD
VNTH
∆VTN
VTP
∆VTP
F
CONDITIONS
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
1, 2, 3, 4
+25
o
C
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
TEMPERATURE
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
+25
o
C
MIN
-
-2.8
-
0.2
-
VOH >
VDD/2
-
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25
o
C
Limit
UNITS
µA
V
V
V
V
V
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25
o
C limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25
o
C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
IOL5
IOH5A
±
1.0µA
±
20% x Pre-Test Reading
±
20% x Pre-Test Reading
DELTA LIMIT
7-1311
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