MACH 1 and 2 CPLD Families
High-Performance EE CMOS Programmable Logic
FEATURES
x
x
x
x
x
x
x
x
x
x
x
x
x
High-performance electrically-erasable CMOS PLD families
32 to 128 macrocells
44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages
SpeedLocking™ – guaranteed fixed timing up to 16 product terms
Commercial 5/5.5/6/7.5/10/12/15-ns t
PD
and Industrial 7.5/10/12/14/18-ns t
PD
Configurable macrocells
— Programmable polarity
— Registered or combinatorial outputs
— Internal and I/O feedback paths
— D-type or T-type flip-flops
— Output Enables
— Choice of clocks for each flip-flop
— Input registers for MACH 2 family
JTAG (IEEE 1149.1)-compatible, 5-V in-system programming available
Peripheral component interconnect (PCI) compliant at 5/5.5/6/7.5/10/12 ns
Safe for mixed supply voltage system designs
Bus-Friendly™ inputs and I/Os reduce risk of unwanted oscillatory outputs
Programmable power-down mode results in power savings of up to 75%
Supported by Vantis DesignDirect™ software for rapid logic development
— Supports HDL design methodologies with results optimized for Vantis
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
Lattice/Vantis and third-party hardware programming support
— Lattice/VantisPRO™ (formerly known as MACHPRO
®
) software for in-system programmability
support on PCs and Automated Test Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
Publication#
14051
Amendment/0
Rev:
K
Issue Date:
November 1998
Table 1. MACH 1 and 2 Family Device Features
1
Feature
Macrocells
Maximum user I/O pins
t
P D
(ns)
t
S
(ns)
t
CO
(ns)
f
CNT
(MHz)
MACH111 (SP)
32
32
5.0
3.5
3.5
182
MACH131 (SP)
64
64
5.5
3.0
4
182
MACH211 (SP)
64
32
7.5 (6.0)
5.5 (5)
4.5 (4)
133 (166)
MACH221 (SP)
96
48
7.5
5.5
5
133
MACH231 (SP)
128
64
6.0 (10)
5 (6.5)
4 (6.5)
166 (100)
Note:
1. Values in parentheses ( ) are for the SP version.
GENERAL DESCRIPTION
The MACH
®
1 & 2 families from Lattice/Vantis offer high-performance, low cost Complex
Programmable Logic Devices (CPLDs), addressing the growing need for speed in networking,
telecommunications and computing. MACH 1 & 2 devices are available in speeds as fast as 5.0-ns
t
PD
and in densities ranging from 32 to 128 macrocells (Tables 1 and 2). The overall benefits for
users include guaranteed high performance for entry-to-mid-level logic needs at a low cost.
Table 2. MACH 1 and 2 Family Speed Grades
1
Device
MACH111
MACH111SP
MACH131
MACH131SP
MACH211
MACH211SP
MACH221
MACH221SP
MACH231
MACH231SP
Notes:
1. C = Commercial, I = Industrial
2. -5 speed grade for MACH111 (SP) = 5.0 ns t
PD
3. -5 speed grade for MACH131(SP) = 5.5 ns t
PD
C
C
-5
C (Note 2)
C (Note 2)
C (Note 3)
C (Note 3)
-6
-7
C, I
C, I
C, I
C, I
C
C
C
C
C
-10
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C
C
-12
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
C, I
-14
I
I
I
I
I
I
I
I
I
I
-15
C
C
C
C
C
C
C
C
C
C
-18
I
I
I
I
I
I
I
I
I
I
The MACH 1 & 2 families consist of ten devices—five base options, each with a counterpart that
includes JTAG-compatible in-system programming (ISP). These devices offer five different density-
I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), and Plastic
Leaded Chip Carrier (PLCC) packages from 44 to 100 pins (Table 3). Each MACH 1 & 2 device is
PCI compliant and includes other features such as SpeedLocking architecture for guaranteed fixed
timing, Bus-Friendly inputs and I/Os, and programmable power-down mode for extra power
savings.
2
MACH 1 & 2 Families
Table 3. MACH 1 and 2 Family Package and I/O Options
Device
MACH111
MACH111SP
MACH131
MACH131SP
MACH211
MACH211SP
MACH221
MACH221SP
MACH231
MACH231SP
X
X
X
X
X
X
X
X
X
44-pin PLCC
X
X
44-pin TQFP
X
X
X
X
X
68-pin PLCC
84-pin PLCC
100-pin TQFP
100-pin PQFP
Note:
1. The MACH110, MACH120, MACH130, MACH210, MACHLV210, MACH215, MACH220 and MACH230 are not listed above and
not recommended for new designs. However, they are still supported by Lattice/Vantis. For technical or sales support, please call
your local Lattice/Vantis sales office or visit our Web site at www.vantis.com for more information.
Lattice/Vantis offers software design support for MACH devices in both the MACHXL
®
and
DesignDirect development systems. The DesignDirect development system is the Lattice/Vantis
implementation software that includes support for all Lattice/Vantis CPLD, FPGA, and SPLD
devices. This system is supported under Windows ’95, ’98 and NT as well as Sun Solaris and HPUX.
DesignDirect software is designed for use with design entry, simulation and verification software
from leading-edge tool vendors such as Cadence, Exemplar Logic, Mentor Graphics, Model
Technology, Synopsys, Synplicity, Viewlogic and others. It accepts EDIF 2 0 0 input netlists,
generates JEDEC files for Lattice/Vantis PLDs and creates industry-standard EDIF, Verilog, VITAL
compliant VHDL and SDF simulation netlists for design verification.
DesignDirect software is also available in product configurations that include VHDL and Verilog
synthesis from Exemplar Logic and VHDL, Verilog RTL and gate level timing simulation from Model
Technology. Schematic capture and ABEL entry, as well as functional simulation, are also provided.
MACH 1 & 2 Families
3
FUNCTIONAL DESCRIPTION
Each MACH 1 and 2 device consists of multiple, optimized PAL
®
blocks interconnected by a switch
matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL
blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs
in a single device instead of using multiple devices.
Clock/Input Pins
Output
Macrocells
Array and
Allocator
I/O Pins
PAL Block
Buried
Macrocells
Buried Macrocell Feedback
Output Macrocell Feedback
I/O Pin Feedback
(note 1)
I/O Cells
I/O Pins
PAL Block
I/O Pins
PAL Block
Switch Matrix
PAL Block
I/O Pins
14051K-002
Note:
1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells.
Device
MACH111(SP)
MACH131(SP)
MACH211(SP)
MACH221(SP)
MACH231(SP)
PAL Blocks
2
4
4
8
8
Macrocells per Block
16
16
16
12
16
I/Os per Block
16
16
8
6
8
Product Terms per Block
70
70
68
52
68
Dedicated Input
Figure 1. Overall Architecture of MACH 1 & 2 Devices
The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes
them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must
go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices
communicate with each other with guaranteed fixed timing (SpeedLocking).
The switch matrix makes a MACH device more advanced than simply several PAL devices on a
single chip. It allows the designer to think of the device not as a collection of blocks, but as a
single programmable device; the software partitions the design into PAL blocks through the
central switch matrix so that the designer does not have to be concerned with the internal
architecture of the device.
4
MACH 1 & 2 Families
Each PAL block consists of the following elements:
x
Product-term array
x
Logic Allocator
x
Macrocells
x
I/O cells
Each PAL block additionally contains an asynchronous reset product term and an asynchronous
preset product term. This allows the flip-flops within a single PAL block to be initialized as a bank.
There are also output enable product terms that provide tri-state control for the I/O cells.
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic being
implemented. The inputs to the AND gates come from the switch matrix (Table 4), and are
provided in both true and complement forms for efficient logic implementation.
Because the number of product terms available for a given function is not fixed, the full sum of
products is not realized in the array. The product terms drive the logic allocator, which allocates
the appropriate number of product terms to generate the function.
Table 4. PAL Block Inputs
Device
MACH111
MACH111SP
MACH131
MACH131SP
MACH211
Number of Inputs to PAL Block
26
26
26
26
26
MACH221
MACH221SP
MACH231
MACH231SP
Device
MACH211SP
Number of Inputs to PAL Block
26
26
26
32
32
Logic Allocator
The logic allocator (Figure 2) is a block within which different product terms are allocated to the
appropriate macrocells in groups of four product terms called “product term clusters”. The
availability and distribution of product term clusters is automatically considered by the software as
it fits functions within the PAL block. The size of the product term clusters has been designed to
provide high utilization of product terms. Complex functions using many product terms are
possible, and when few product terms are used, there will be a minimal number of unused, or
wasted, product terms left over.
The product term clusters do not “wrap” around the logic block. This means that the macrocells
at the ends of the block have fewer product terms available (Tables 5, 6, 7, 8).
MACH 1 & 2 Families
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
