HV9606
HV9606 Current-Mode PWM Controller
3.3V, 5V Operation (No Bootstrap needed)
Features
Synchronous Forward, Forward, and Flyback Controller
Lowest External Parts Count, Smallest Magnetics
Eliminates Bootstrap Transformer Winding
Supervisor Circuit Reduces Output Capacitance* up to 40%
Supervisor Circuit Functions as
µP
Supply Monitor and POR
15V to 250V Start-Up Regulator with START/STOP Control
<1mA Operating, <6µA Standby Input Current
V
DD
Powered Operation down to 2.9V
Charge Pump Gate Drive Supply
Programmable Soft Start
Under Voltage Lockout with Programmable Hysteresis
<50% Duty Cycle Operation
15kHz to 300kHz Fixed Frequency PWM Operation
Fault Tolerant Peer-to-Peer Synchronization
Precision
±1%
Band Gap Voltage Reference
Current Sense Leading Edge Blanking
Small SSOP-20 Footprint
*For short duration line loss, supervisor disables soft start if output
within tolerance when V
IN
returns and thus reduces holdup
requirements.
General Description
The HV9606 PWM controller allows the design of high efficiency
(>90%) power supplies for distributed board mounted power (BMP)
applications. Due to its low internal operating voltage and current,
the HV9606 is able to achieve high efficiencies in low power
applications.
The HV9606 utilizes fixed frequency current mode control with duty
cycle internally limited to <50%. It supports both isolated and non-
isolated topologies and provides all the necessary functions to
implement a flyback, forward or synchronous forward converter
with a minimum of external parts. Due to its low V
DD
operation the
bootstrap magnetic winding is eliminated in non-isolated
topologies. An on chip charge pump generates the gate drive
voltage for driving an external N-channel MOSFET and eliminates
the need for clamping by offering 250V immunity to high voltage
transients common in telecom and network systems. It conforms
to the requirements of IEEE 802.3 Powered Ethernet and ETR-080
ISDN specifications.
The oscillator is programmable and provides fault tolerant peer-to-
peer synchronization to other similar circuits or master clock. The
chip draws almost no current (<6µA @ V
IN
< 20V) until the
programmable START/STOP thresholds of the start-up regulator
are satisfied. It can also be powered via the V
DD
pin, rather than
the V
IN
pin, in the range of 2.9V to 5.5V.
Other functions include leading edge current sense blanking,
programmable SOFT START, precision
±1%
band gap reference
and a SUPERVISOR CIRCUIT. The SUPERVISOR can provide
housekeeping functions such as
µP
supply monitoring and reset,
soft start inhibit for rapid restart on short duration input voltage
interruption. It also minimizes input and output capacitance
requirements.
Applications
Powered Ethernet and VoIP Terminals
Cable Modems and Amplifiers
ISDN Network Terminations, Terminals and Adapters
Network Equipment
Servers, PCs and Peripheral Equipment
Telecommunication Systems and Terminals
Distributed Board Mounted Power
Battery Backup Systems
Portable Power Applications
Automotive and Heavy Equipment
Typical Application Circuit
10W Non-Isolated 48V to 3.3V Flyback Converter
R3
R2
C2
C9
1
VDD
STATUS
20
Q1
2
START
SENSE
19
To uP
RESET
Pin.
R1
+48V
C4
3
STOP
FB
18
C7
C8
R6
T1
D1
C10
+3.3V
R7
5
HV9606
4
Vin
COMP
17
REF
NI
16
6
SS
CA
15
C3
7
SYNC
C6
CB
14
VX2
13
C1
R4
8
RT
R8
C5
M1
R9
R5
R10
9
SGND
GATE
12
10
PGND
CS
11
GND
To SYNC pin of other HV9606 PWMs.
GND
HV9606
A022205
Electrical Characteristics
Symbol
Parameter
(T
A
= +25
°
C unless otherwise noted)
Min
Typ
Max
Units
Conditions
Pre-Regulator/Start-up
V
IN
I
IN
I
IN
V
DD(REG)
UVLO
VDD
UVLO
VDD
Regulator input voltage
Input leakage current
Input leakage current
Regulator output voltage
V
DD
Under voltage lockout threshold
V
DD
Under voltage lockout hysteresis
2.8
2.7
100
2.9
2.8
15
250
6
50
3.0
2.9
250
V
µA
µA
V
V
mV
V
IN
= 20V, Start = 0V, Stop = 0V
V
IN
= 250V
Vin < 120V
V
DD
rising
Supply
V
DD
I
DD
V
VX2
UVLO
VX2
(Test Condition: 0.1
µ
F CA to CB and 0.1
µ
F VX2 to PGND)
Operating range
Supply current
Gate drive charge pump supply
VX2 Under voltage lockout threshold
1.8V
DD
4.5
2.9
1.0
5.5
1.5
V
mA
V
V
GATE open, f
OSC
= 50 kHz, V
DD
= 3.3V
Start/Stop Control
V
START
V
STOP(MAX)
V
STOP
I
START
I
STOP
Start threshold
Maximum voltage
Stop threshold
Start input current
Stop input current
(Test condition: V
VX2
= 5V)
V
VX2
-0.2
0.15
30
30
50
50
V
V
nSec
nSec
I
GATE
= 10mA
I
GATE
= -10mA
C
LOAD
= 250pF
C
LOAD
= 250pF
6.44
7.00
6.44
7.00
7.56
13
7.56
50
50
V
V
V
nA
nA
V
IN
falling, V
START
= 0V
6.44V
≤
V
START
≤
7.56V, V
STOP
is open
6.44
≤
V
STOP
≤
7.56V, V
START
to 10V via 10k
V
IN
rising
MOSFET Driver Output
V
GATE(HIGH)
V
GATE(LOW)
t
R
t
F
Output high voltage
Output low voltage
Rise time
Fall time
Oscillator
f
OSC
f
OSCRANGE
T
C
∆f/f
Initial accuracy
Oscillator Frequency Range
Temperature coefficient
Voltage stability
30
100
10
600
300
15
%
kHz
PPM/ºC f
OSC
= 100 kHz
%
f
OSC
= 100 kHz, 2.9V
≤
V
DD
≤
5.5V
SYNC
I
OSYNC
I
ISYNC
I
VSYNC
Sync output current
Sync input current
Sync input voltage absolute limits
10
-0.5
V
DD
+0.5
10
20
µA
µA
V
V
SYNC
< 0.1 Volt
PWM
F
PWM
D
MAX
D
MIN
D
MIN
D
MIN
PWM Oscillation Frequency
Maximum duty cycle
Minimum pulse width before pulse drop out
Minimum duty cycle
Minimum duty cycle
15
49
130
195
0
0
300
kHz
%
nSec
%
%
F
PWM
= f
OSC
/2, Stability as f
OSC
above
f
OSC
= 600kHz
V
DD
= 3.3V
V
FB
> V
NI
, V
SS
> 2V
V
FB
< V
NI
, V
SS
< 0.1V
2
HV9606
Electrical Characteristics –
continued
Symbol
Parameter
Min
Typ
Max
Units
Test Conditions
Reference
V
REF
V
REF
V
REF
V
REF
V
REF
I
REF(SHORT)
Reference output voltage
Reference output voltage tolerance
Reference output voltage tolerance
Load regulation
Line regulation
Short circuit current
(Test conditions: V
DD
= 3.3V)
0
0.48V
REF
0.50V
REF
85
70
120
0.69
0.52V
REF
V
V
nSec
nSec
V
CS
= 0 to 1V step after blanking time
T
A
= 25°C
T
A
= 25°C
2
2
1.2402
1
2
5
5
3
V
%
%
mV
mV
mA
2.9V
≤
V
DD
≤
5.5V
2.9V
≤
V
DD
≤
5.5V
-40ºC
≤
T
A
≤
+85ºC, 2.9V
≤
V
DD
≤
5.5V
0 < I
REF
< 0.1 mA
2.9V
≤
V
DD
≤
5.5V
V
REF
= GND
Current Sensing
V
CS
V
CS
V
CS
t
DELAY
Usable control current sense range
Current limit threshold
Leading edge current sense blanking
time
Current limit delay to output
Error Amplifier
I
FB
or I
NI
V
FB
- V
NI
V
CM
A
VOL
BW
I
SOURCE
I
SINK
V
COMP
PSRR
(Test conditions: 2.9V
≤
V
DD
≤
5.5V)
25
0
65
1
1
-100
0
50
V
DD
–0.7
2
200
±3
V
DD
–0.1
nA
mV
V
dB
MHz
mA
µA
V
dB
F
OSC
= 100 kHz
V
FB
< V
NI
V
FB
> V
NI
V
FB
= 1.5V, V
NI
= V
REF
V
FB
= V
COMP
, V
NI
= V
REF
Input bias current
Input offset voltage
Common mode input range
Open loop voltage gain
Unity gain bandwidth
Output current sourcing
Output current sinking
Output voltage range
Power supply rejection
Soft Start
V
SS(LOW)
V
SS(HI)
I
SS(HI)
t
F
Soft start low output
Soft start high output
Soft start output current
Soft start output fall time
(Test conditions: 3.3V
≤
V
DD
≤
5.5V)
2
10
V
DD
-0.1
0.85V
REF
+ 0.050
0.85V
REF
- 0.100
100
0.85V
REF
+ 0.075
0.85V
REF
- 0.075
150
20
V
DD
0.85V
REF
+ 0.100
0.85V
REF
- 0.050
200
mA
µA
V
V
V
mV
V
OL_STATUS
= 0.2V
V
STATUS
= (V
DD
- 0.5V)
No load
V
STATUS
= LOW to HIGH transition
V
STATUS
= HIGH to LOW transition
2.5
10
0.1
V
DD
20
10
V
V
µA
µSec
V
DD
= 2.9V, V
SENSE
= 0V, V
CS
= 2.9V
V
DD
= 2.9V, V
SENSE
= 2.9V, V
CS
= 2.9V
V
DD
= 2.9V, V
SENSE
= 2.9V, V
CS
= 2.9V
C
SS
= 0.1µF
Status Output
I
SINK
I
SOURCE
Output current sinking
Output current sourcing
V
STATUS(HIGH)
High output voltage
V
SENSE(THLH)
V
SENSE(THHL)
V
SENSE(HYST)
Sense input threshold for rising input
Sense input threshold for falling input
Sense input hysteresis
3
HV9606
Absolute Maximum Ratings*
V Input Voltage
-0.3V to +250V
-0.3V to +6V
Supply Voltage, V
DD
Gate Drive Supply Voltage, VX2
-0.3 to +15V
Operating Ambient Temperature Range -40°C to +85°C
Storage Temperature Range
-65°C to +150°C
Power Dissipation @ 25°C, SSOP
750mW
* Absolute Maximum Ratings are those values beyond which damage to device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect reliability. All voltages referenced to
SGND and PGND pins
Ordering Information
Package Option
20-Pin SSOP
HV9606SP
__________________________________________________________________________________________________________________
Pinout
VDD
START
STOP
Vin
REF
SS
SYNC
RT
SGND
PGND
1
20
STATUS
SENSE
FB
COMP
NI
CA
CB
VX2
GATE
CS
2
19
3
18
HV9606
4
17
SYNC –
This I/O pin may be connected to the SYNC pin of other
HV9606 circuits and will cause the oscillators to lock to the highest
frequency oscillator. Synchronization to a master clock is possible
by means of an open collector or open drain logic gate or
optocoupler, provided the low duty cycle does not exceed 50%. If
synchronization is utilized then a pull up resistor to V
DD
is required
to overcome the effects of parasitic capacitance on the circuit
board. The value of the resistor required will depend on the
operating frequency and master clock duty cycle.
RT –
The resistor connected from this pin to SGND sets the
frequency of the internal oscillator by setting the charging current
for the internal timing capacitor. The PWM output frequency is one
half the oscillator frequency.
SGND –
Common connection for all Logic and Analog circuits.
PGND –
Common connection for Gate Driver circuit.
CS –
This is the current sense input. Under normal operation the
over current limit is triggered when the voltage on this pin exceeds
0.5*V
REF
, however, current sensing is blanked during the first 85ns
on time of the MOSFET to prevent false triggering during the turn
on switching transition. The loop control operating peak current
sense may be set to any level below 0.5*V
REF
.
GATE –
This push-pull CMOS output is designed to drive the gate
of an N-Channel power MOSFET.
VX2 –
This is the supply pin for the Gate Driver circuit and is
generated by the Charge Pump V
DD
voltage doubler circuit. It
should be bypassed to PGND with a capacitor, typically 0.1µF.
CA and CB –
The charge pump circuit uses a capacitor (typically
0.01µF) connected between these pins to generate the VX2
voltage.
NI –
High impedance non-inverting input of the error amplifier.
COMP –
The output of the error amplifier.
FB –
High impedance inverting input of the error amplifier.
SENSE –
This is the input pin to the supervisory circuit. On a
rising input voltage the circuit changes state at a nominal 0.85V
REF
+ 0.075V. When the input voltage is decaying the circuit changes
state a nominal 0.85V
REF
– 0.075V.
STATUS
– This is the output of the supervisory circuit. When the
sense-input voltage is high, this output is pulled up to V
DD
by a
10µA current source and the Soft Start function is disabled. When
the sense-input is low, this output is pulled low and it may be used
to directly control the reset of a microprocessor or it may be used
to drive an optocoupler or LED indicator.
5
16
6
15
7
14
8
13
9
12
10
11
Pin Description
V
DD
–
This is the supply pin for the PWM Logic and Analog circuits.
When the input voltage to the V
IN
pin exceeds the start voltage the
input regulator seeks to regulate the voltage on the capacitor
connected to this pin to a nominal 2.9V. After the PWM has
started, the bootstrap supply will regulate this voltage to a nominal
3.3V or 5V. With V
IN
connected to PGND the circuit can be
powered via this pin in the voltage range of 2.9V to 5.5V with a
nominal 2.8V UVLO.
START
– The resistive divider from V
IN
sets the start-up regulator
start voltage.
STOP
– The resistive divider from V
IN
sets the start-up regulator
stop voltage.
A low power sleep mode function may be
implemented by pulling this pin to SGND.
V
IN
–
This is the startup linear regulator input. It can accept DC
input voltages in the range of 15V to 250V. With START and
STOP programmed to more than 20V, the leakage current on this
pin is less than 6µA at V
IN
= 20V.
VREF –
This pin provides a
±1%
tolerance reference voltage.
SS
– A capacitor connected to this pin determines the soft start
time. Soft start may be initiated by a low VX2 voltage or an over
current condition when supervisor circuit STATUS output is low.
During short duration input interruptions when the output voltage
does not decay below programmed limits, the supervisor circuit
inhibits soft start to permit rapid recovery of the system.
4
HV9606
Functional Block Diagram
Vin
Regulator Start-Up
Enable Regulator
Programable
Start/Stop
Circuit
Vdd
Vdd
UVLO
C
Oscillator
Enable
CA
VX2
UVLO
C
VX2
Voltage
Doubler
CB
STOP
START
Oscillator
CLK Q
_
D ___ Q
CLR
A
C
GATE
S
Q
CS
R
R
PGND
Soft
Start
Supervisor Enable
Circuit
R
Soft
Start
Circuit
R
C
Current
Limit
SGND
Vdd
Bandgap
Reference
Generator
85 nS Delay
RT
SYNC STATUS SENSE
SS
VREF
NI
FB
COMP
Functional Description
The HV9606 is composed of several functional blocks. The
operation of each of these blocks is described in the following
sections.
Programmable Start/Stop Control Circuit
(Programmable Under Voltage Lockout and Hysteresis)
The START/STOP control circuit is a novel version of a
programmable under voltage lockout with programmable
hysteresis circuit. It is novel, because it requires zero power (other
than the current in the resistor divider) and keeps the startup
regulator shut down until the START threshold voltage is
exceeded, allowing the HV9606 to achieve its low input leakage
current of <6µA.
One can think of the circuit as a transparent latch, such that its
output is high when the START pin is above its threshold voltage
and is latched when the STOP pin is at a voltage greater than the
START pin voltage. It is unlatched when the STOP pin voltage
falls below its threshold voltage and the START pin is below its
threshold voltage.
These operating conditions are met by using a voltage divider
consisting of three resistors (see typical application circuit). The
voltage drop on the resistor connected to ground controls the
START voltage and the additional voltage drop on the middle
resistor sets the hysteresis and controls the STOP voltage. Setting
the value of the middle resistor to zero results in zero hysteresis.
Provided the START and STOP pin input currents are negligible in
comparison to the chosen resistor divider current, the resistor
values may be calculated using the following equations:
R3 = (V
START
/ V
IN-Start
) x (V
IN-Stop
/ I
Resistor
)
R2 = [(V
STOP
/ V
IN-Stop
) x (V
IN-Stop
/ I
Resistor
)] – R3
R1 = (V
IN-Operating
/ I
Resistor
) - R2 - R3
Where:
V
START
is the START pin threshold voltage (nominal 7V)
V
STOP
is the STOP pin threshold voltage (nominal 7V)
V
IN-Start
is the input voltage at which starting is desired
V
IN-Stop
is the input voltage at which shutdown is desired
I
Resistor
is the resistor divider current (>1µA)
5
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