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74LCX112M_Q

产品描述触发器 J-K neg flip-flop
产品类别半导体    其他集成电路(IC)   
文件大小98KB,共9页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
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74LCX112M_Q概述

触发器 J-K neg flip-flop

74LCX112M_Q规格参数

参数名称属性值
厂商名称Fairchild
RoHS
电路数量Dual
逻辑系列74LC
逻辑类型D-Type Flip-Flops
极性Inverting/Non-Inverting
输入类型Single-Ended
输出类型Differential
传播延迟时间8 ns @ 2.7 V
高电平输出电流- 24 mA
低电平输出电流24 mA
电源电压(最大值)3.6 V
最大工作温度85 C
安装风格SMD/SMT
封装 / 箱体SOIC-16
封装Tube
最小工作温度- 40 C
电源电压(最小值)2 V

文档预览

下载PDF文档
74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
June 1998
Revised February 2001
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs
s
2.3V–3.6V V
CC
specifications provided
s
7.5 ns t
PD
max (V
CC
=
3.3V), 10
µ
A I
CC
max
s
Power down high impedance inputs and outputs
s
±
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine model
>
2000V
Ordering Code:
Order Number
74LCX112M
74LCX112SJ
74LCX112MTC
Package Number
M16A
M16D
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
, Q
2
Description
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active LOW)
Direct Set Inputs (Active LOW)
Outputs
© 2001 Fairchild Semiconductor Corporation
DS012424
www.fairchildsemi.com

74LCX112M_Q相似产品对比

74LCX112M_Q 74LCX112MTC_Q
描述 触发器 J-K neg flip-flop 触发器 J-K neg flip-flop
厂商名称 Fairchild Fairchild
RoHS
电路数量 Dual Dual
逻辑系列 74LC 74LC
逻辑类型 D-Type Flip-Flops J-K Negative Edge-Triggered Flip-Fl
极性 Inverting/Non-Inverting Inverting/Non-Inverting
输入类型 Single-Ended Single-Ended
输出类型 Differential Differential
传播延迟时间 8 ns @ 2.7 V 8 ns @ 2.7 V
高电平输出电流 - 24 mA - 24 mA
低电平输出电流 24 mA 24 mA
电源电压(最大值) 3.6 V 3.6 V
最大工作温度 85 C 85 C
安装风格 SMD/SMT SMD/SMT
封装 / 箱体 SOIC-16 TSSOP-16
封装 Tube Tube
最小工作温度 - 40 C - 40 C
电源电压(最小值) 2 V 2 V

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