Obsolete Device
24LCS61/24LCS62
1K/2K Software Addressable I
2
C
™
Serial EEPROM
Device Selection Table
Device
24LCS51
24LCS62
Array
Size
1K bits
2K bits
Voltage
Range
2.5V-5.5V
2.5V-5.5V
Software Write
Protection
Entire Array
Lower Half
EDS
Vss
3
4
Package Types
PDIP
NC
NC
1
24LCS61/62
2
8
7
6
5
8
7
6
5
8
7
6
5
Vcc
NC
SCL
SDA
Features
• Low-power CMOS technology
- 1 mA active current typical
- 10
µA
standby current typical at 5.5V
• Software addressability allows up to 255 devices
on the same bus
• 2-wire serial interface bus, I
2
C compatible
• Automatic bus arbitration
• Wakes up to control code 0110
• General purpose output pin can be used to enable
other circuitry
• 100 kHz and 400 kHz compatibility
• Page write buffer for up to 16 bytes
• 10 ms max write cycle time for byte or page write
• 1,000,000 erase/write cycles
• 8-pin PDIP, SOIC or TSSOP packages
• Temperature ranges supported:
- Industrial (I):
-40°C to +85°C
SOIC
NC
NC
EDS
Vss
TSSOP
NC
NC
EDS
V
SS
1
2
3
4
1
2
3
4
V
CC
NC
SCL
SDA
24LCS61/62
24LCS61/62
Vcc
NC
SCL
SDA
Block Diagram
EDS
HV Generator
Memory
Control
Logic
I/O
Control
Logic
XDEC
EEPROM
Array
ID Register
Serial Number
Description
The Microchip Technology Inc. 24LCS61/62 is a 1K/2K
bit Serial EEPROM developed for applications that
require many devices on the same bus but do not have
the I/O pins required to address each one individually.
These devices contain an 8 bit address register that is
set upon power-up and allows the connection of up to
255 devices on the same bus. When the process of
assigning ID values to each device is in progress, the
device will automatically handle bus arbitration if more
than one device is operating on the bus. In addition, an
external open drain output pin is available that can be
used to enable other circuitry associated with each
individual system. Low current design permits
operation with typical standby and active currents of
only 10
µA
and 1 mA respectively. The device has a
page write capability for up to 16 bytes of data. The
device is available in the standard 8-pin PDIP, SOIC
(150 mil), and TSSOP packages.
I
2
C is a trademark of Philips Corporation.
SDA SCL
V
CC
V
SS
YDEC
Sense Amp.
R/W Control
Pin Function Table
Name
V
SS
SDA
SCL
V
CC
NC
EDS
Ground
Serial Data
Serial Clock
+2.5V to 5.5V Power Supply
No Internal Connection
External Device Select Output
Function
2004 Microchip Technology Inc.
DS21226E-page 1
24LCS61/24LCS62
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-65°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= +2.5V to +5.5V
Industrial (I): T
A
= -40°C to +85°C
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CC
Read
I
CCS
Min.
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
—
Max.
—
.3 V
CC
—
.40
±1
±1
10
4
1
50
Units
V
V
V
V
µA
µA
pF
mA
mA
µA
I
OL
= 12 mA, V
CC
= 4.5V
I
OL
= 8 mA, V
CC
= 2.5V
V
IN
= Vss or Vcc
V
OUT
= Vss or Vcc
V
CC
= 5.0V
(Note)
T
A
= 25°C, f = 1 MHz
V
CC
= 5.5V
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V, SDA = SCL = V
CC
EDS = V
CC
Conditions
All parameters apply across the
specified operating ranges unless
otherwise noted.
Parameter
SCL and SDA pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger
inputs
Low-level output voltage
(SDA and EDS pins)
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note:
This parameter is periodically sampled and not 100% tested.
DS21226E-page 2
2004 Microchip Technology Inc.
24LCS61/24LCS62
TABLE 1-2:
AC CHARACTERISTICS
Vcc = +2.5V to 5.5V
Industrial (I): T
A
= -40°C to +85°C
All parameters apply across the specified
operating ranges unless otherwise noted.
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
V
CC
= 2.5V - 5.5V Vcc = 4.5V - 5.5V
STD MODE
FAST MODE
Symbol
Min.
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Remarks
From V
IL
to V
IH
(Note 1)
From V
IL
to V
IH
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
Start condition
(Note 2)
T
OF
Output fall time
(from 0.7 V
CC
to 0.3 V
CC
)
Input filter spike suppression T
SP
(SDA and SCL pins)
Write cycle time
T
WC
Endurance
Note 1:
2:
3:
4:
—
—
—
1M
250
50
10
—
20 +0.1
C
B
—
—
1M
250
50
10
—
ns
ns
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1),
C
B
≤
100 pF
(Notes 1, 3)
ms Byte or Page mode
cycles 25°C, V
CC
= 5.0V, Block
mode
(Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from our web site.
FIGURE 1-1:
BUS TIMING DATA
T
F
T
HIGH
T
R
SCL
Tsu:sta
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
SP
T
HD
:
STA
T
AA
SDA
OUT
T
BUF
2004 Microchip Technology Inc.
DS21226E-page 3
24LCS61/24LCS62
2.0
2.1
PIN DESCRIPTIONS
SDA (Serial Data)
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The SDA pin has Schmitt Trigger and filter circuits
which suppress noise spikes to assure proper device
operation even on a noisy bus
3.1
Bus not Busy (A)
Both data and clock lines remain high.
2.2
SCL (Serial Clock)
3.2
Start Data Transfer (B)
This input is used to synchronize the data transfer from
and to the device. The SCL pin has Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
2.3
EDS (External Device Select)
3.3
Stop Data Transfer (C)
The External Device Select (EDS) pin is an open drain
output that is controlled by using the OE bit in the
control byte. It can be used to enable other circuitry
when the device is selected. A pull-up resistor must be
added to this pin for proper operation. This pin should
not be pulled up to a voltage higher than Vcc+1V. See
Section 9.0 “External Device Select (EDS) Pin and
Output Enable (OE) Bit”
for more details.
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
FIGURE 3-1:
SCL
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(D)
(D)
(C)
(A)
SDA
START
CONDITION
DATA OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
DS21226E-page 4
2004 Microchip Technology Inc.
24LCS61/24LCS62
3.5
Acknowledge
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24LCS61/62 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition (Figure 3-2).
FIGURE 3-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
2004 Microchip Technology Inc.
DS21226E-page 5
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