TN5325
N-Channel Enhancement-Mode
Vertical DMOS FET
Features
►
Low threshold (2.0V max.)
►
High input impedance and high gain
►
Free from secondary breakdown
►
Low C
ISS
and fast switching speeds
General Description
This low threshold, enhancement-mode (normally-off)
transistor utilizes a vertical DMOS structure and Supertex’s
well-proven, silicon-gate manufacturing process. This
combination produces a device with the power handling
capabilities of bipolar transistors and the high input impedance
and positive temperature coefficient inherent in MOS devices.
Characteristic of all MOS structures, this device is free
from thermal runaway and thermally-induced secondary
breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide
range of switching and amplifying applications where very
low threshold voltage, high breakdown voltage, high input
impedance, low input capacitance, and fast switching speeds
are desired.
Applications
►
Logic level interfaces - ideal for TTL and CMOS
►
Solid state relays
►
►
►
►
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
►
Telecom switches
Ordering Information
Device
TN5325
Package Options
TO-236AB (SOT-23)
TN5325K1-G
TO-92
TN5325N3-G
TO-243AA (SOT-89)
TN5325N8-G
BV
DSS
/BV
DGS
(V)
R
DS(ON)
(max)
(Ω)
I
D(ON)
(min)
(A)
V
GS(th)
(max)
(V)
250
7.0
1.2
2.0
-G indicates package is RoHS compliant (‘Green’)
Pin Configurations
Absolute Maximum Ratings
Parameter
Drain-to-source voltage
Drain-to-gate voltage
Gate-to-source voltage
Operating and storage temperature
Soldering temperature*
O
DRAIN
Value
BV
DSS
BV
DGS
±20V
-55 C to +150 C
O
GATE
DRAIN
SOURCE
SOURCE
TO-236AB (SOT-23) (K1)
DRAIN
TO-92 (N3)
GATE
300
O
C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
*
Distance of 1.6mm from case for 10 seconds.
GATE
SOURCE
DRAIN
TO-243AA (SOT-89) (N8)
SiTN
5325
YYWW
YY = Year Sealed
WW = Week Sealed
= “Green” Packaging
Product Marking
N3CW
W = Code for week sealed
= “Green” Packaging
TN3CW
W = Code for week sealed
= “Green” Packaging
TO-236AB (SOT-23) (K1)
TO-92 (N3)
TO-243AA (SOT-89) (N8)
Packages may or may not include the following marks: Si or
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
TN5325
Thermal Characteristics
Package
TO-236AB (SOT-23)
TO-92
TO-243AA (SOT-89)
(continuous)
(mA)
I
D
†
(pulsed)
(A)
I
D
Power Dissipation
@T
A
= 25
O
C
(W)
O
( C/W)
θ
jc
( C/W)
O
θ
ja
(mA)
I
DR
†
I
DRM
(A)
150
215
316
0.4
0.8
1.5
0.36
0.74
1.6
‡
200
125
15
350
170
78
‡
150
215
316
0.4
0.8
1.5
Notes:
† I
D
(continuous) is limited by max rated T
j
.
‡ Mounted on FR5 Board, 25mm x 25mm x 1.57mm.
Electrical Characteristics
(T
Sym
BV
DSS
V
GS(th)
ΔV
GS(th)
I
GSS
Parameter
A
= 25
O
C unless otherwise specified)
Min
250
0.6
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300
Max
-
2.0
-4.5
100
1.0
10
1.0
-
-
8.0
7.0
1.0
-
110
60
23
20
15
25
25
1.8
-
Units
V
V
nA
µA
mA
A
Ω
%/
O
C
Conditions
V
GS
= 0V, I
D
= 100µA
V
GS
= V
DS
, I
D
= 1.0mA
V
GS
= ± 20V, V
DS
= 0V
V
GS
= 0V, V
DS
= 100V
V
GS
= 0V, V
DS
= Max Rating
V
DS
= 0.8 Max Rating,
V
GS
= 0V, T
A
= 125°C
V
GS
= 4.5V, V
DS
= 25V
V
GS
= 10V, V
DS
= 25V
V
GS
= 4.5V, I
D
= 150mA
V
GS
= 10V, I
D
= 1.0A
V
GS
= 4.5V, I
D
= 150mA
Drain-to-source breakdown voltage
Gate threshold voltage
Change in V
GS(th)
with temperature
Gate body leakage
mV/
O
C V
GS
= V
DS
, I
D
= 1.0mA
I
DSS
Zero gate voltage drain current
I
D(ON)
R
DS(ON)
ΔR
DS(ON)
G
FS
C
ISS
C
OSS
C
RSS
t
d(ON)
t
r
t
d(OFF)
t
f
V
SD
t
rr
On-state drain current
Static drain-to-source
on-state resistance
Change in R
DS(ON)
with temperature
Forward transductance
Input capacitance
Common source output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
Turn-off delay time
Fall time
Diode forward voltage drop
Reverse recovery time
0.6
1.2
-
-
-
150
-
-
-
-
-
-
-
-
-
mmho V
DS
= 25V, I
D
= 200mA
pF
V
GS
= 0V,
V
DS
= 25V,
f = 1.0MHz
ns
V
DD
= 25V,
I
D
= 150mA,
R
GEN
= 25Ω
V
GS
= 0V, I
SD
= 200mA
V
GS
= 0V, I
SD
= 200mA
V
ns
Notes:
1. All D.C. parameters 100% tested at 25
O
C unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.)
2. All A.C. parameters sample tested.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
TN5325
Switching Waveforms and Test Circuit
V
DD
10V
90%
10%
t
(ON)
INPUT
0V
PULSE
GENERATOR
t
(OFF)
t
r
t
d(OFF)
t
F
R
L
OUTPUT
t
d(ON)
V
DD
R
GEN
10%
90%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
TN5325
3-Lead TO-236AB (SOT-23) Package Outline (K1)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
Top View
View B
View B
Side View
View A - A
Symbol
Dimension
(mm)
MIN
NOM
MAX
A
0.89
-
1.12
A1
0.01
-
0.10
A2
0.88
0.95
1.02
b
0.30
-
0.50
D
2.80
2.90
3.04
E
2.10
-
2.64
E1
1.20
1.30
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20
†
0.50
0.60
L1
0.54
REF
θ
0
O
-
8
O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO236ABK1, Version C041309.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
TN5325
3-Lead TO-92 Package Outline (N3)
D
A
Seating Plane
1
2
3
L
e1
e
b
c
Front View
Side View
E1
E
1
2
3
Bottom View
Symbol
Dimensions
(inches)
MIN
NOM
MAX
A
.170
-
.210
b
.014
†
-
.022
†
c
.014
†
-
.022
†
D
.175
-
.205
E
.125
-
.165
E1
.080
-
.105
e
.095
-
.105
e1
.045
-
.055
L
.500
-
.610*
JEDEC Registration TO-92.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc.#:
DSPD-3TO92N3, Version E041009.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
