24AA65/24LC65/24C65
64K I
2
C
™
Smart Serial
™
EEPROM
Device Selection Table
Part Number
24AA65
24LC65
24C65
V
CC
Range
1.8-6.0V
2.5-6.0V
4.5-6.0V
Page Size
64 Bytes
64 Bytes
64 Bytes
Temp. Ranges
C
C, I
C, I, E
Packages
P, SM
P, SM
P, SM
Features
• Voltage operating range: 1.8V to 6.0V
- Peak write current 3 mA at 6.0V
- Maximum read current 150
µA
at 6.0V
- Standby current 1
µA
typical
• Industry standard two-wire bus protocol I
2
C™
compatible
• 8-byte page, or byte modes available
• 2 ms typical write cycle time, byte or page
• 64-byte input cache for fast write loads
• Up to 8 devices may be connected to the same
bus for up to 512K bits total memory
• Including 100 kHz (1.8V
≤
Vcc
<
4.5V) and 400
kHz (4.5V
≤
V
CC
≤
6.0V) compatibility
• Programmable block security options
• Programmable endurance options
• Schmitt Trigger, filtered inputs for noise
suppression
• Output slope control to eliminate ground bounce
• Self-timed erase and write cycles
• Power-on/off data protection circuitry
• Endurance:
- 10,000,000 E/W cycles for a High Endurance
Block
- 1,000,000 E/W cycles for a Standard
Endurance Block
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP/SOIC packages
• Temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I)
-40°C to +85°C
- Automotive (E)
-40°C to +125°C
Description
The Microchip Technology Inc. 24AA65/24LC65/
24C65 (24XX65)* is a “smart” 8K x 8 Serial Electrically
Erasable PROM. This device has been developed for
advanced, low-power applications such as personal
communications, and provides the systems designer
with flexibility through the use of many new user-pro-
grammable features. The 24XX65 offers a relocatable
4K bit block of ultra-high-endurance memory for data
that changes frequently. The remainder of the array, or
60K bits, is rated at 1,000,000 erase/write (E/W) cycles
ensured. The 24XX65 features an input cache for fast
write loads with a capacity of eight pages, or 64 bytes.
This device also features programmable security
options for E/W protection of critical data and/or code
of up to fifteen 4K blocks. Functional address lines
allow the connection of up to eight 24XX65's on the
same bus for up to 512K bits contiguous EEPROM
memory. Advanced CMOS technology makes this
device ideal for low-power nonvolatile code and data
applications. The 24XX65 is available in the standard
8-pin plastic DIP and 8-pin surface mount SOIC
package.
Package Types
PDIP
A0
A1
A2
V
SS
1
8
V
CC
NC
SCL
SDA
24XX65
2
3
4
7
6
5
SOIC
A0
A1
A2
1
8
V
CC
NC
SCL
SDA
24XX65
2
3
4
7
6
5
*24XX65 is used in this document as a generic part
number for the 24AA65/24LC65/24C65 devices.
V
SS
2003 Microchip Technology Inc.
DS21073J-page 1
24AA65/24LC65/24C65
Block Diagram
A0 A1 A2
HV Generator
Pin Function Table
Name
A0, A1, A2
V
SS
SDA
SCL
V
CC
NC
Function
User Configurable Chip Selects
Ground
Serial Address/Data/I/O
Serial Clock
+1.8V to 6.0V Power Supply
No Internal Connection
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
SCL
Cache
SDA
V
CC
V
SS
YDEC
Sense Amp.
R/W Control
DS21073J-page 2
2003 Microchip Technology Inc.
24AA65/24LC65/24C65
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. V
SS
..........................................................................................................-0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
†
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= +1.8V to +6.0V
Commercial
(C): T
A
=
Industrial
(I): T
A
=
Automotive
(E): T
A
=
Sym
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
Write
I
CC
Read
I
CCS
Min
.7 V
CC
—
.05 V
CC
—
—
—
—
—
—
—
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Max
—
.3 V
CC
—
.40
±1
±1
10
3
150
5
Units
V
V
V
V
µA
µA
pF
mA
µA
µA
Conditions
DC CHARACTERISTICS
Parameter
A0, A1, A2, SCL and SDA pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
Standby current
Note 1:
(Note 1)
I
OL
= 3.0 mA
V
IN
= .1V to V
CC
V
OUT
= .1V to V
CC
V
CC
= 5.0V
(Note 1)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 6.0V, SCL = 400 kHz
V
CC
= 6.0V, SCL = 400 kHz
V
CC
= 5.0V, SCL = SDA = V
CC
A0, A1, A2 = V
SS
This parameter is periodically sampled and not 100% tested.
FIGURE 1-1:
BUS TIMING START/STOP
V
HYS
SCL
T
SU
:
STA
SDA
T
HD
:
STA
T
SU
:
STO
S
TART
S
TOP
2003 Microchip Technology Inc.
DS21073J-page 3
24AA65/24LC65/24C65
TABLE 1-2:
AC CHARACTERISTICS
V
CC
= 1.8V-6.0V
STD. Mode
Symbol
Min
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max
100
—
—
1000
300
—
—
—
—
—
3500
—
V
CC
= 4.5-6.0V
FAST Mode
Min
—
600
1300
—
—
600
600
0
100
600
—
1300
Max
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Remarks
Parameter
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for
repeated Start condition
Output fall time from V
IH
min to T
OF
—
250
20 + 0.1
250
ns
V
IL
max
C
B
50
—
50
—
ns
(Note 3)
Input filter spike suppression
T
SP
(SDA and SCL pins)
—
5
—
5
ms/page
(Note 4)
Write cycle time
T
WR
Endurance
High Endurance Block
10M
—
10M
—
cycles 25°C,
(Note 5)
Rest of Array
1M
—
1M
—
Note 1:
Not 100 percent tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
4:
The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
5:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.
(Note 2)
Time the bus must be
free before a new
transmission can start
(Note 1),
C
B
≤
100 pF
FIGURE 1-2:
BUS TIMING DATA
T
F
T
HIGH
T
LOW
T
R
SCL
T
SU
:
STA
T
HD
:
STA
SDA
IN
T
SP
T
AA
SDA
OUT
T
AA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
BUF
DS21073J-page 4
2003 Microchip Technology Inc.
24AA65/24LC65/24C65
2.0
FUNCTIONAL DESCRIPTION
3.3
Stop Data Transfer (C)
The 24XX65 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus must be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the Start
and Stop conditions, while the 24XX65 works as slave.
Both master and slave can operate as transmitter or
receiver, but the master device determines which mode
is activated.
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
3.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24XX65 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
3.1
Bus not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX65) must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
(A)
(B)
(D)
(D)
(C)
(A)
SDA
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
To Change
Stop
Condition
2003 Microchip Technology Inc.
DS21073J-page 5
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