NB2304A
3.3 V Zero Delay
Clock Buffer
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute high-
-speed clocks in PC, workstation, datacom, telecom
and other high-
-performance applications. It is available in an 8 pin
package. The part has an on-
-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
input- -output propagation delay is guaranteed to be less than
-to-
250 ps, and the output- -output skew is guaranteed to be less than
-to-
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304AI1 is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304AI1H is the high-
-drive version of
the - and the rise and fall times on this device are much faster.
-1
The NB2304AI2 allows the user to obtain REF, 1/2 X and 2X
frequencies on each output Bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
Features
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MARKING
DIAGRAM*
8
8
1
SOIC-
-8
D SUFFIX
CASE 751
1
XXXX
ALYW
G
XXXX
A
L
Y
W
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb--Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Zero Input -- Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
Multiple Configurations - Refer to NB2304A Configurations Table
-
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low-
-Skew Outputs
Output-
-Output Skew < 200 ps
Device-
-Device Skew < 500 ps
Two Banks of Four Outputs
Less than 200 ps Cycle- -Cycle Jitter (- -
-to-
-1, -1H, -
-5H)
Available in Space Saving, 8 pin 150 mil SOIC Package
3.3 V Operation
Advanced 0.35
m
CMOS Technology
Guaranteed Across Commercial and Industrial Temperature Ranges
These are Pb-
-Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Semiconductor Components Industries, LLC, 2010
October, 2010 - Rev. 9
-
1
Publication Order Number:
NB2304A/D
NB2304A
FBK
CLKA1
REF
PLL
CLKA2
÷2
Extra Divider (--2)
CLKB1
CLKB2
Figure 1. Basic Block Diagram
(see Figures 11 and 12 for device specific Block Diagrams)
Table 1. CONFIGURATIONS
Device
NB2304AI1
NB2304AI1H
NB2304AI2
NB2304AI2
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A Frequency
Reference
Reference
Reference
2 X Reference
Bank B Frequency
Reference
Reference
Reference
÷2
Reference
REF
CLKA1
CLKA2
GND
1
2
8
7
FBK
V
DD
CLKB2
CLKB1
Table 2. PIN DESCRIPTION
Pin #
1
2
3
4
5
Pin Name
REF (Note 1)
CLKA1 (Note 2)
CLKA2 (Note 2)
GND
CLKB1 (Note 2)
CLKB2 (Note 2)
V
DD
FBK
Description
Input reference frequency, 5 V
tolerant input.
Buffered clock output, Bank A.
Buffered clock output, Bank A.
Ground.
Buffered clock output, Bank B.
Buffered clock output, Bank B.
3.3 V supply.
PLL feedback input.
NB2304A
3
4
6
5
Figure 2. Pin Configuration
6
7
8
1. Weak pulldown.
2. Weak pulldown on all outputs.
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2
NB2304A
Table 3. MAXIMUM RATINGS
Parameter
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
Storage Temperature
Maximum Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (per MIL--STD--883, Method 3015)
Min
--0.5
--0.5
--0.5
--65
Max
+7.0
V
DD
+ 0.5
7
+150
260
150
> 2000
Unit
V
V
V
C
C
C
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. OPERATING CONDITIONS
Parameter
V
DD
T
A
C
L
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance, 15 MHz to 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance (Note 3)
Industrial
Commercial
Description
Min
3.0
--40
0
Max
3.6
85
70
30
15
7
Unit
V
C
pF
pF
pF
3. Applies to both REF Clock and FBK.
Table 5. ELECTRICAL CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Supply Current
V
IN
= 0 V
V
IN
= V
DD
I
OL
= 8 mA (--1, --2)
I
OL
= 12 mA (--1H)
I
OH
= --8 mA (--1, --2)
I
OH
= --12 mA (--1H)
Unloaded outputs 100 MHz REF
Select inputs at V
DD
or GND
Unloaded outputs, 66 MHz REF (--1, --2)
Unloaded outputs, 33 MHz REF (--1, --2)
2.4
45
35
20
2.0
50.0
100.0
0.4
Test Conditions
Min
Max
0.8
Unit
V
V
mA
mA
V
V
mA
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3
NB2304A
(All parameters are specified with loaded outputs)
Parameter
t
1
t
1
Description
Output Frequency
Duty Cycle = (t
2
/ t
1
) * 100
(all devices)
Table 6. SWITCHING CHARACTERISTICS
V
CC
= 3.0 V to 3.6 V, GND = 0 V, T
A
= --40C to +85C
Test Conditions
30 pF load (all devices)
15 pF load (--1, --2)
Measured at 1.4 V, F
OUT
≤
66.66 MHz
30 pF load
Measured at 1.4 V, F
OUT
≤
50 MHz
15 pF load
t
3
Output Rise Time
(--1, --2)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Output Rise Time
(--1H)
t
4
Output Fall Time
(--1, --2)
Measured between 0.8 V and 2.0 V
30 pF load
Measured between 2.0 V and 0.8 V
30 pF load
Measured between 2.0 V and 0.8 V
15 pF load
Output Fall Time
(--1H)
t
5
Output--to--Output Skew on same Bank
(--1, --2)
Output--to--Output Skew
(--1H)
Output Bank A--to--Output Bank B skew
(--1)
Output Bank A--to--Output Bank B skew
(--2)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to FBK Rising
Edge
Device--to--Device Skew
Output Slew Rate
Cycle--to--Cycle Jitter
(--1, --1H)
Measured between 2.0 V and 0.8 V
30 pF load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of the
device
Measured between 0.8 V and 2.0 V using
Test Circuit #2
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
Cycle--to--Cycle Jitter
(--2)
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
t
LOCK
PLL Lock Time
Stable power supply, valid clock presented
on REF and FBK pins
1
180
200
100
400
380
1.0
ms
ps
0
0
Min
15
15
40.0
45.0
50.0
50.0
Typ
Max
100
133.3
60.0
55.0
2.50
1.50
1.50
2.50
1.50
1.25
200
200
200
400
250
500
ps
ps
V/ns
ps
ps
ns
ns
Unit
MHz
%
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NB2304A
Zero Delay and Skew Control
For applications requiring zero input-
-output delay, all
outputs must be equally loaded.
1500
REF INPUT TO CLKA/CLKB DELAY (ps)
1000
500
0
--500
--1000
--1500
--30 --25 --20 --15 --10
To close the feedback loop of the NB2304A, the FBK pin
can be driven from any of the four available output pins. The
output driving the FBK pin will be driving a total load of
7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input output delay. This is shown in Figure 3.
For applications requiring zero input-
-output delay, all
outputs including the one providing feedback should be
equally loaded. If input-
-output delay adjustments are
required, use Figure 3 to calculate loading differences
between the feedback output and remaining outputs. For
zero output-
-output skew, be sure to load outputs equally.
--5
0
5
10
15
20
25
30
OUTPUT LOAD DIFFERENCE: FBK LOAD -- CLKA/CLKB LOAD (pF)
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
SWITCHING WAVEFORMS
t
1
t
2
1.4 V
1.4 V
1.4 V
2.0 V
OUTPUT
0.8 V
t
3
2.0 V
0.8 V
t
4
0V
3.3 V
Figure 4. Duty Cycle Timing
Figure 5. All Outputs Rise/Fall Time
OUTPUT
OUTPUT
1.4 V
1.4 V
t
5
INPUT
OUTPUT
t
6
V
DD
2
V
DD
2
Figure 6. Output - Output Skew
-
Figure 7. Input - Output Propagation Delay
-
FBK_Device 1
FBK_Device 2
t
7
V
DD
2
V
DD
2
Figure 8. Device - Device Skew
-
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