TMPN3120FE3MG
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TMPN3120FE3MG
Neuron
®
Chip for Distributed Intelligent Control Networks (L
ON
W
ORKS
®
)
The TMPN3120FE3MG features extra single-chip memory in the form of
a 2 Kbyte EEPROM, a 2 Kbyte SRAM, and a 16 Kbyte ROM.
Neuron Chips have all the built-in communications and control functions
®
required to implement L
ON
W
ORKS
nodes. These nodes may then be easily
integrated into highly reliable distributed intelligent control networks.
The typical functions for this chip are described below.
Features
Main features of the 20 MHz Neuron Chip
(compared with the TMPN3120E1M)
•
Increased communication speed
The maximum transmission speed has been increased twofold:
1.25 Mbps
→
2.5 Mbps (This value applies to Single-Ended
Mode only.)
Weight: 1.1 g (typ.)
•
Shortened response time
The amount of time required from I/O input to I/O output has been greatly reduced.
Maximum speed:
7 ms
→
3 to 4 ms
•
Increased I/O object speed
The execution time for all objects has been halved.
Example)
Serial I/O 9600 bps
Parallel I/O 1.2 µs/byte
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TMPN3120FE3MG
I/O functions
•
Eleven programmable I/O pins
•
Two programmable 16-bit timers and counters built in
•
More than thirty different types of I/O functions to handle a wide range of input and output
•
ROM firmware image containing preprogrammed I/O drivers, greatly simplifying application programs
Network functions
•
Two CPUs for communication protocol processing built in
The communications and application CPUs execute in parallel.
•
Equipped with a built-in LonTalk protocol supporting all seven levels of the ISO OSI reference model
•
The ROM firmware image contains a complete network operating system, greatly simplifying application programs.
•
Built-in twisted-pair wire transceiver
•
Equipped with communications modes and communication speeds to support various types of external
transceivers
•
Communication port transceiver modes and logical addresses are stored within the EEPROM.
Can be amended via the network.
Other functions
•
Application programs are also stored within the EEPROM.
Can be updated by downloading over the network.
•
Built-in watchdog timer
•
Each chip has a unique ID number.
Effective during the logical installation of networks
•
Low electrical consumption mode supported through a sleep mode
•
Reset time
Prolongs the power-on reset time for at least 50 ms and keeps the operation stable during that time.
•
High-impedance communication port (CP0 to CP3) when powered down
The communication port pins (CP0 to CP3) attain high impedance when the Neuron Chip is powered down.
This feature eliminates the need for an external relay.
•
Built-in low-voltage detection circuit
Prevents incorrect operations and writing errors in the EEPROM during drops in power voltage.
An external LVD must be used to assert reset at a power supply voltage below 4.5 V if the Neuron Chip is
operated at 20 MHz.
•
The package is SOP32-P-525-1.27 (lead-free type).
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TMPN3120FE3MG
Timing for the main I/O objects during 20 MHz Neuron Chip operations
I/O Model
Parallel
Bitshift
Magcard
Magtrack1
Neurowire master
Neurowire slave
Serial
Touch
Frequency output
2.4 µs/byte
10 MHz Timing
1.2 µs/byte
20 MHz Timing
1, 10 or 15 kbps
Up to 8334 bps
Up to 7246 bps
1, 10 or 20 kbps
Up to 18 kbps
600, 1200, 2400 or 4800 bps
Supported
Resolution: 0.4 to 51.2 µs
Max range: 26.21 to 3355 ms
Resolution: 0.2 to 25.6 µs
Max range: 13.1 to 1678 ms
2, 20 or 30 kbps
Up to 16668 bps
Up to 14492 bps
2, 20 or 40 kbps
Up to 36 kbps
1200, 2400, 4800 or 9600 bps
Not supported
Resolution: 0.2 to 25.6 µs
Max range: 13.1 to 1678 ms
Resolution: 0.1 to 12.8 µs
Max range: 6.55 to 839 ms
Other timer/counter
The specifications for the main timers during 20 MHz operations are as follows:
Watchdog timer
Millisecond timers
Second timers
Delay ( ) function
Get_tick_count ( ) function
420 ms
1 to 32000 ms
1 to 65000 s
1 to 32767 counts
409.6 µs per count
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TMPN3120FE3MG
Block Diagram
Network
communications
port
• Application I/O
• General-purpose I/O
• Parallel I/O
• Serial I/O
• Two timer/counters
Etc.
Clock and control
50 ms reset
(min)
Low-voltage
detector reset
circuit
Item
CPU
RAM
ROM
EEPROM
16-bit timer/counter
External memory interface
Package
TMPN3120FE3MG
8-bit CPU × 3
2,048 bytes
16,384 bytes
2,048 bytes
2 channels
Not available
32-pin SOP
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TMPN3120FE3MG
Pin Connections
TMPN3120FE3MG
Note: All NC pins should be open.
Pin Functions
Pin No.
15
14
1
Pin Name
CLK1
CLK2
~RESET
I/O
Input
Output
I/O
(built-in pull-up)
I/O
(built-in configurable
pull-up)
I/O
Pin Function
Oscillator connection, or external clock input
Oscillator connection. Leave open when the external
clock is input to CLK1.
Reset pin (active low)
8
~SERVICE
Service pin. Indicator output during operation.
Large current sink capacity (20 mA)
General I/O port.
General I/O port. One of IO
4
to IO
7
can be specified as
the No.1 timer/counter input.
Output signals can be output to IO
0
.
IO
4
can be used as the No.2 timer/counter input with
IO
1
as output.
General I/O port. Can be used for serial communication
with other devices.
Power input (5.0 V typ.)
Power input (0 V GND)
Bidirectional port for communications. Supports several
communications protocols through specifying of mode.
Do not connect anything. Leave pins open.
7 to 4
IO
0
to IO
3
3, 30 to 28
IO
4
to IO
7
I/O
(built-in configurable
pull-up)
27, 26, 24
2, 11, 12, 18, 25, 32
9, 10, 13, 16, 23, 31
19, 20, 17, 21, 22
―
IO
8
to IO
10
V
DD
V
SS
CP
0
to CP
4
NC
I/O
Input
Input
I/O
―
Note:
●
The ~SERVICE and IO
4
to IO
7
terminals are programmable pull-ups.
●
All V
DD
terminals must be externally connected.
●
All V
SS
terminals must be externally connected.
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