74VHC4316 Quad Analog Switch with Level Translator
May 2007
74VHC4316
Quad Analog Switch with Level Translator
Features
■
Typical switch enable time: 20ns
■
Wide analog input voltage range: ±6V
■
Low “ON” resistance: 50 Typ. (V
CC
–V
EE
=
4.5V)
■
■
■
■
tm
General Description
These devices are digitally controlled analog switches
implemented in advanced silicon-gate CMOS technol-
ogy. These switches have low “ON” resistance and low
“OFF” leakages. They are bidirectional switches, thus
any analog input may be used as an output and vice-
versa. Three supply pins are provided on the 4316 to
implement a level translator which enables this circuit to
operate with 0V–6V logic levels and up to ±6V analog
switch levels. The 4316 also has a common enable input
in addition to each switch's control which when HIGH will
disable all switches to their off state. All analog inputs
and outputs and digital inputs are protected from electro-
static damage by diodes to V
CC
and ground.
30 Typ. (V
CC
–V
EE
=
9V)
Low quiescent current: 80µA maximum (74VHC)
Matched switch characteristics
Individual switch controls plus a common enable
Pin functional compatible with 74HC4316
Ordering Information
Order Number
74VHC4316M
74VHC4316WM
74VHC4316MTC
Package
Number
M16A
M16B
MTC16
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the
ordering number.
Connection Diagram
Truth Table
Inputs
E
H
L
L
Switch
CTL
X
L
H
I/O–O/I
“OFF”
“OFF”
“ON”
Top View
©1994 Fairchild Semiconductor Corporation
74VHC4316 Rev. 1.2
www.fairchildsemi.com
74VHC4316 Quad Analog Switch with Level Translator
Logic Diagram
©1994 Fairchild Semiconductor Corporation
74VHC4316 Rev. 1.2
www.fairchildsemi.com
2
74VHC4316 Quad Analog Switch with Level Translator
Absolute Maximum Ratings
(1)
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
V
EE
V
IN
V
IO
I
IK
, I
OK
I
OUT
I
CC
T
STG
P
D
T
L
Supply Voltage
Supply Voltage
DC Control Input Voltage
DC Switch I/O Voltage
Clamp Diode Current
DC Output Current, per pin
Parameter
Rating
–0.5 to +7.5V
+0.5 to –7.5V
–1.5 to V
CC
+1.5V
V
EE
–0.5 to V
CC
+0.5V
±20mA
±25mA
±50mA
–65°C to +150°C
600mW
500mW
260°C
DC V
CC
or GND Current, per pin
Storage Temperature Range
Power Dissipation
S.O. Package only
Lead Temperature (Soldering 10 seconds)
Note:
1. Unless otherwise specified all voltages are referenced to ground.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
V
EE
V
IN
, V
OUT
T
A
t
r
, t
f
Supply Voltage
Supply Voltage
Parameter
Min.
2
0
0
–40
Max.
6
–6
V
CC
+85
Units
V
V
V
°C
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
V
CC
=
2.0V
V
CC
=
4.5V
V
CC
=
6.0V
V
CC
=
12.0V
1000
500
400
250
ns
©1994 Fairchild Semiconductor Corporation
74VHC4316 Rev. 1.2
www.fairchildsemi.com
3
74VHC4316 Quad Analog Switch with Level Translator
DC Electrical Characteristics
(2)
T
A
=
25°C
Symbol
V
IH
T
A
=
–40°C
to +85°C
1.5
3.15
4.2
0.5
1.35
1.8
200
105
85
215
100
75
60
20
15
15
±1.0
±300
±500
±75
±150
nA
µA
nA
Ω
Ω
V
V
Parameter
Minimum HIGH Level
Input Voltage
Conditions
V
EE
V
CC
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
Typ.
Guaranteed Limits Units
1.5
3.15
4.2
0.5
1.35
1.8
V
IL
Maximum LOW Level
Input Voltage
R
ON
Minimum “ON”
Resistance
(3)
V
CTL
=
V
IH
,
I
S
=
2.0mA,
V
IS
=
V
CC
to V
EE
,
(Fig. 1)
V
CTL
=
V
IH
,
I
S
=
2.0mA,
V
IS
=
V
CC
or V
EE
(Fig. 1)
GND
–4.5V
–6.0V
GND
GND
–4.5V
–6.0V
GND
–4.5V
–6.0V
GND
GND
–6.0V
GND
–6.0V
4.5V
4.5V
6.0V
2.0V
4.5V
4.5V
6.0V
4.5V
4.5V
6.0V
6.0V
6.0V
6.0V
6.0V
6.0V
100
40
30
100
40
50
20
10
5
5
170
85
70
180
80
60
40
15
10
10
±0.1
±30
±50
±20
±30
R
ON
Maximum “ON”
Resistance Matching
V
CTL
=
V
IH
,
V
IS
=
V
CC
to V
EE
V
IN
=
V
CC
or GND
V
OS
=
V
CC
or V
EE
,
V
IS
=
V
EE
or V
CC
,
V
CTL
=
V
IL
(Fig. 2)
V
IS
=
V
CC
to V
EE
,
V
CTL
=
V
IH
,
V
OS
=
OPEN
(Fig. 3)
V
IN
=
V
CC
or GND,
I
OUT
=
0 µA
I
IN
I
IZ
Maximum Control Input
Current
Maximum Switch “OFF”
Leakage Current
Maximum Switch “ON”
Leakage Current
I
IZ
I
CC
Maximum Quiescent
Supply Current
GND
–6.0V
6.0V
6.0V
1.0
4.0
10
40
µA
Notes:
2. For a power supply of 5V ±10% the worst case on resistances (R
ON
) occurs for VHC at 4.5V. Thus the 4.5V values
should be used when designing with this supply. Worst case V
IH
and V
IL
occur at V
CC
=
5.5V and 4.5V respectively.
(The V
IH
value at 5.5V is 3.85V.) The worst case leakage current occurs for CMOS at the higher voltage and so the
5.5V values should be used.
3. At supply voltages (V
CC
–V
EE
) approaching 2V the analog switch on resistance becomes extremely non-linear.
Therefore it is recommended that these devices be used to transmit digital only when using these supply voltages.
©1994 Fairchild Semiconductor Corporation
74VHC4316 Rev. 1.2
www.fairchildsemi.com
4
74VHC4316 Quad Analog Switch with Level Translator
AC Electrical Characteristics
V
CC
=
2.0V – 6.0V, V
EE
=
0V – 6V, C
L
=
50 pF unless otherwise specified
T
A
=
+25°C
Symbol
t
PHL
, t
PLH
T
A
=
–40°C
to +85°C
37
13
12
11
120
43
39
37
180
63
55
55
150
52
48
45
190
67
59
59
MHz
ns
ns
ns
ns
ns
Parameter
Maximum Propagation
Delay Switch In to Out
Conditions
V
EE
GND
GND
–4.5V
–6.0V
V
CC
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
3.3V
4.5V
4.5V
6.0V
4.5
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
4.5V
Typ.
15
5
4
3
25
20
15
14
35
25
20
20
27
20
19
18
42
28
23
21
40
100
100
250
–52
–50
–42
–44
Guaranteed Limits
Units
30
10
8
7
97
35
32
30
145
50
44
44
120
41
38
36
155
53
47
47
t
PZL
, t
PZH
Maximum Switch Turn
“ON” Delay (Control)
R
L
=
1kΩ
GND
GND
–4.5V
–6.0V
t
PHZ
, t
PLZ
Maximum Switch Turn
“OFF” Delay (Control)
R
L
=
1 kΩ
GND
GND
–4.5V
–6.0V
t
PZL
, t
PZH
Maximum Switch Turn
“ON” Delay (Enable)
GND
GND
–4.5V
–6.0V
t
PLZ
, t
PHZ
Maximum Switch Turn
“OFF” Delay (Enable)
GND
GND
–4.5V
–6.0V
Minimum Frequency
Response (Fig. 7)
20 log (V
OS
/V
IS
)= –3 dB
Control to Switch
Feedthrough Noise
(Fig. 8)
Crosstalk Between any
Two Switches (Fig. 9)
Switch OFF Signal
Feedthrough Isolation
(Fig. 10)
THD
Sinewave Harmonic
Distortion
R
L
=
600Ω,
V
IS
=
2V
PP
at
(V
CC
–V
EE
/2)
(4)(5)
R
L
=
600Ω, f
=
1MHz
C
L
=
50pF
(5)(6)
R
L
=
600Ω, f
=
1MHz
R
L
=
600Ω,
f
=
1MHz,
V
CTL
=
V
IL(5)(6)
R
L
=
10 KΩ,
C
L
=
50 pF, f
=
1KHz
V
IS
=
4 V
PP
V
IS
=
8 V
PP
0V
–4.5V
0V
–4.5V
0V
–4.5V
0V
–4.5V
mV
dB
dB
0V
–4.5V
4.5V
4.5V
0.013
0.008
5
35
%
pF
pF
pF
pF
C
IN
C
IN
C
IN
C
PD
Maximum Control Input
Capacitance
Maximum Switch Input
Capacitance
Maximum Feedthrough
Capacitance
Power Dissipation
Capacitance
V
CTL
=
GND
0.5
15
Notes:
4. Adjust 0 dBm for f
=
1 kHz (Null R
L
/Ron Attenuation).
5. V
IS
is centered at V
CC
–V
EE
/2.
6. Adjust for 0 dBm.
©1994 Fairchild Semiconductor Corporation
74VHC4316 Rev. 1.2
www.fairchildsemi.com
5
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