Si5330
1 . 8 / 2 . 5 / 3 . 3 V L
O W
J
I T T E R
, L
O W
S
K E W
C
L O C K
B
U F F E R
/ L
E V E L
T
R A N S L A T O R
Features
18
17
16
15
14
13
7
8
9
10
11
12
Supports single-ended or
differential input clock signals
Generates four differential
(LVPECL, LVDS, HCSL) or eight
single-ended (CMOS, SSTL,
HSTL) outputs
Provides signal level translation
Differential to single-ended
Single-ended to differential
Differential to differential
Single-ended to single-ended
Wide frequency range
LVPECL, LVDS: 5 to 710 MHz
HCSL: 5 to 250 MHz
SSTL, HSTL: 5 to 350 MHz
CMOS: 5 to 200 MHz
Additive jitter: 150 fs RMS typ
RSVD_GND
CLK0A
CLK0B
VDDO0
20
Small size: 24-lead, 4 x 4 mm
QFN
VDD
24
23
22
21
OEB
19
Output-output skew: 100 ps
Propagation delay: 2.5 ns typ
Single core supply with excellent
PSRR: 1.8, 2.5, or 3.3 V
Output driver supply voltage
independent of core supply: 1.5,
1.8, 2.5, or 3.3 V
Loss Of Signal (LOS) indicator
allows system clock monitoring
Output Enable (OEB) pin allows
glitchless control of output clocks
Low power: 10 mA typical core
current
Industrial temperature range:
–40 to +85
°
C
Ordering Information:
See page 14.
Pin Assignments
IN1
IN2
IN3
CLK1A
CLK1B
VDDO1
VDDO2
CLK2A
CLK2B
1
Applications
2
3
High Speed Clock Distribution
Ethernet Switch/Router
SONET / SDH
PCI Express 2.0/3.0
Fibre Channel
MSAN/DSLAM/PON
Telecom Line Cards
GND
GND
RSVD_GND
RSVD_GND
RSVD_GND
4
5
Functional Block Diagram
V
DD
V
DDO0
CLK0
Si5330
V
DDO1
CLK1
Single-ended
or
Differential
IN
V
DDO2
CLK2
Single-ended
or
Differential
V
DDO3
LOS
OEB
Control
CLK3
Rev. 0.35 5/10
Copyright © 2010 by Silicon Laboratories
RSVD_GND
LOS
VDDO3
VDD
CLK3B
CLK3A
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
6
Si5330
Si5330
1. Functional Block Diagrams Based on Orderable Part Number
*
1:4 Differential to Differential Buffer
Si5330A/B/C
V
DDO0
CLK0A
CLK0B
IN1
IN2
IN3
V
DDO1
CLK1A
CLK1B
V
DDO2
CLK2A
CLK2B
LOS
OEB
Control
V
DDO3
CLK3A
CLK3B
LOS
OEB
Control
IN1
IN2
IN3
1:8 Single-Ended to Single-Ended Buffer
Si5330F
V
DDO0
CLK0A
CLK0B
V
DDO1
CLK1A
CLK1B
V
DDO2
CLK2A
CLK2B
V
DDO3
CLK3A
CLK3B
1:8 Differential to Single-Ended Buffer
Si5330G/H/J
V
DDO0
CLK0A
CLK0B
IN1
IN2
IN3
V
DDO1
CLK1A
CLK1B
V
DDO2
CLK2A
CLK2B
LOS
OEB
1:4 Single-Ended to Differential Buffer
Si5330K/L/M
V
DDO0
CLK0A
CLK0B
IN3
IN1
IN2
V
DDO1
CLK1A
CLK1B
V
DDO2
CLK2A
CLK2B
LOS
OEB
Control
V
DDO3
CLK3A
CLK3B
Control
V
DDO3
CLK3A
CLK3B
Figure 1. Si5330 Functional Block Diagrams
*Note:
See Table 10 for detailed ordering information.
2
Rev. 0.35
Si5330
T
ABLE
Section
OF
C
ONTENTS
Page
1. Functional Block Diagrams Based on Orderable Part Number* . . . . . . . . . . . . . . . . . . .2
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.1. VDD and VDDO Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2. Loss Of Signal Indicator (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3. Output Enable (OEB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4. Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5. Output Driver Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6. Input and Output Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4. Ordering the Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5. Pin Descriptions—Si5330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6. Orderable Part Numbers and Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7. Package Outline: 24-Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Rev. 0.35
3
Si5330
2. Electrical Specifications
Table 1. Recommended Operating Conditions
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Ambient Temperature
Symbol
T
A
Test Condition
Min
–40
2.97
Typ
25
3.3
2.5
1.8
—
Max
85
3.63
2.75
1.98
3.63
Unit
°C
V
V
V
V
Core Supply Voltage
V
DD
2.25
1.71
Output Buffer Supply
Voltage
V
DDOn
1.4
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Table 2. Absolute Maximum Ratings
Parameter
DC Supply Voltage
Storage Temperature Range
ESD Tolerance
ESD Tolerance
ESD Tolerance
Latch-up Tolerance
Symbol
V
DD
T
STG
Test Condition
Value
–0.5 to 3.8
–55 to 150
Unit
V
°C
kV
V
V
HBM
(100 pF, 1.5 k)
CDM
MM
2.5
550
175
JESD78 Compliant
Note:
Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
4
Rev. 0.35
Si5330
Table 3. DC Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Core Supply Current
Symbol
I
DD
Test Condition
50 MHz refclk
LVPECL, 710 MHz
LVDS, 710 MHz
HCSL, 250 MHz
2 pF load capacitance
Min
—
—
—
—
—
—
—
—
Typ
10
—
—
—
—
—
—
—
Max
—
30
8
20
19
28
28
19
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Output Buffer Supply Current
I
DDOx
SSTL, 350 MHz
CMOS, 50 MHz
15 pF load capacitance
CMOS, 200 MHz
2 pF load capacitance
HSTL, 350 MHz
Table 4. Thermal Characteristics
Parameter
Thermal Resistance
Junction to Ambient
Thermal Resistance
Junction to Case
Symbol
JA
JC
Test Condition
Still Air
Still Air
Value
37
25
Unit
°C/W
°C/W
Table 5. Performance Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
CLKIN Loss of Signal Assert
Time
CLKIN Loss of Signal De-Assert
Time
Input-to-Output Propagation
Delay
Output-Output Skew
Symbol
t
LOS
t
LOS_B
t
PROP
t
DSKEW
Test Condition
Min
—
0.01
—
Typ
2.6
0.2
2.5
—
Max
5
1
—
100
Unit
µs
µs
ns
ps
Outputs at same frequency,
signal format
—
Rev. 0.35
5
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