Si5023
M
ULTI
-R
ATE
SONET/SDH CDR IC
WITH
L
IMITING
A
MPLIFIER
Features
H
igh-speed clock and data recovery device with integrated limiting amp:
Supports OC-48/12/3, STM-16/4/
Bit error rate alarm
1, Gigabit Ethernet, and 2.7 Gbps
Reference and referenceless
FEC
operation supported
Loss-of-signal level alarm
DSPLL
®
technology
Data slicing level control
Jitter generation 3.0 mUI
rms
10 mV
PP
differential sensitivity
(TYP)
Small footprint: 5 x 5 mm
3.3 V supply
Ordering Information:
See page 25.
Applications
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Gigabit Ethernet interfaces
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
Board level serial links
Pin Assignments
Si5023
BER_ALM
CLKOUT+
23
Description
RATESEL0
1
2
3
4
5
6
7
28
27
26
25
24
CLKOUT–
22
21
20
19
CLKDSBL
BERMON
BER_LVL
VDD
VDD
REXT
RESET/CAL
VDD
DOUT+
DOUT–
GND
The Si5023 is a fully-integrated, high-performance limiting amp and clock
and data recovery (CDR) IC for high-speed serial communication systems.
It derives timing information and data from a serial input at OC-48/12/3,
STM-16/4/1, or Gigabit Ethernet (GbE) rates. Support for 2.7 Gbps data
streams is also provided for OC-48/STM-16 applications that employ
forward error correction (FEC). Use of an external reference clock is
optional. Silicon Laboratories DSPLL
®
technology eliminates sensitive
noise entry points, thus making the PLL less susceptible to board-level
interaction and helping to ensure optimal jitter performance.
The Si5023 represents a new standard in low jitter, low power, small size,
and integration for high-speed LA/CDRs. It operates from a 3.3 V supply
over the industrial temperature range (–40 to 85 °C).
RATESEL1
LOS_LVL
SLICE_LVL
REFCLK+
REFCLK–
LOL
GND
Pad
18
17
16
15
8
9
10
11
12
13
14
LOS
DIN+
DIN–
VDD
Top View
Functional Block Diagram
LOS_LVL
LOS
Signal
Detect
Retimer
DSQLCH
BUF
2
DOUT+
DOUT–
DIN+
DIN–
2
Limiting
Amp
DSPLL
BER
Monitor
BUF
2
CLKOUT+
CLKOUT–
CLK_DSBL
REFCLK+
REFCLK–
(Optional)
2
Lock
Detection
2
Bias Gen.
Reset/
Calibration
BER_ALM
REXT
BERMON
SLICE_LVL
LTR
BER_LVL
LOL
RATESEL
RESET/CAL
Rev. 1.3 6/08
Copyright © 2008 by Silicon Laboratories
DSQLCH
VDD
LTR
Si5023
Si5023
T
ABLE
Section
OF
C
ONTENTS
Page
1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
3. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.2. DSPLL
® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.3. Multi-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
4.4. Operation Without an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5. Operation With an External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.6. Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.7. Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.8. Loss-of-Signal (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
4.9. Bit Error Rate (BER) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.10. Data Slicing Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.11. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.12. RESET/DSPLL Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13. Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14. Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.15. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.16. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.17. Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.18. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.19. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5. Pin Descriptions: Si5023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Rev. 1.3
3
Si5023
1. Detailed Block Diagram
LOS
BER_LVL
BER_ALM
BERMON
RATESEL[0:1]
LTR
DSQLCH
LOS_LVL
Signal
Detect
BER
Monitor
Retime
DOUT+
DOUT–
DIN+
Limiting
Amp
Phase
Detector
A/D
DSP
n
VCO
CLK
Dividers
CLKOUT+
CLKOUT–
DIN+
SLICE_LVL
Slicing
Control
Lock
Detection
CLKDSBL
REFCLK±
(optional)
Bias
Generation
LOL
REXT
Calibration
RESET/CAL
4
Rev. 1.3
Si5023
2. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Si5023 Supply Voltage
2
Symbol
T
A
V
DD
Test Condition
Min
1
–40
3.135
Typ
25
3.3
Max
1
85
3.465
Unit
°C
V
Notes:
1.
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
2.
The Si5023 specifications are guaranteed when using the recommended application circuit (including component
tolerance) of "3. Typical Application Schematic" on page 11.
V
SIG NAL+
SIG NAL–
V
IS
t
A. Operation with Single-Ended Inputs
V
SIGNAL+
SIGNAL–
0.5 V
ID
(SIGNAL+) – (SIG NAL–)
V
ID
t
B. O peration with Differential Inputs and Outputs
Figure 1. Differential Voltage Measurement (DIN, REFCLK, DOUT, CLKOUT)
t
Cf-D
DOUT
t
C r-D
CLK OUT
Figure 2. Clock to Data Timing
Rev. 1.3
5
电子竞赛
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
