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NSBA123EDXV6T5

产品描述数字晶体管 100ma 50v dual pnp
产品类别分立半导体    晶体管   
文件大小102KB,共11页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
标准
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NSBA123EDXV6T5概述

数字晶体管 100ma 50v dual pnp

NSBA123EDXV6T5规格参数

参数名称属性值
是否Rohs认证符合
厂商名称ON Semiconductor(安森美)
包装说明SMALL OUTLINE, R-PDSO-F6
针数6
制造商包装代码CASE 463A-01
Reach Compliance Codecompli
ECCN代码EAR99
其他特性BUILT IN BIAS RESISTOR RATIO IS 1
最大集电极电流 (IC)0.1 A
集电极-发射极最大电压50 V
配置SEPARATE, 2 ELEMENTS WITH BUILT-IN RESISTOR
最小直流电流增益 (hFE)8
JESD-30 代码R-PDSO-F6
JESD-609代码e3
湿度敏感等级1
元件数量2
端子数量6
封装主体材料PLASTIC/EPOXY
封装形状RECTANGULAR
封装形式SMALL OUTLINE
峰值回流温度(摄氏度)260
极性/信道类型PNP
最大功率耗散 (Abs)0.5 W
认证状态Not Qualified
表面贴装YES
端子面层Tin (Sn)
端子形式FLAT
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
晶体管应用SWITCHING
晶体管元件材料SILICON

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NSBA114EDXV6T1,
NSBA114EDXV6T5 SERIES
Preferred Devices
Dual Bias Resistor
Transistors
PNP Silicon Surface Mount Transistors
with Monolithic Bias Resistor Network
The BRT (Bias Resistor Transistor) contains a single transistor with
a monolithic bias network consisting of two resistors; a series base
resistor and a base−emitter resistor. These digital transistors are
designed to replace a single device and its external resistor bias
network. The BRT eliminates these individual components by
integrating them into a single device. In the NSBA114EDXV6T1
series, two BRT devices are housed in the SOT−563 package which is
ideal for low−power surface mount applications where board space is
at a premium.
Features
(3)
R
1
Q
1
Q
2
R
2
(4)
R
1
(5)
(6)
http://onsemi.com
(2)
R
2
(1)
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
These are Pb−Free Devices
1
SOT−563
CASE 463A
PLASTIC
STYLE 1
MARKING DIAGRAM
MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted, common for Q
1
and Q
2
)
Rating
Collector-Base Voltage
Collector-Emitter Voltage
Collector Current
Symbol
V
CBO
V
CEO
I
C
Value
−50
−50
−100
Unit
Vdc
Vdc
mAdc
xx M
G
G
THERMAL CHARACTERISTICS
Characteristic
(One Junction Heated)
Total Device Dissipation @ T
A
= 25°C
Derate above 25°C (Note 1)
Thermal Resistance, Junction-to-Ambient
(Note 1)
Characteristic
(Both Junctions Heated)
Total Device Dissipation @ T
A
= 25°C
Derate above 25°C (Note 1)
Thermal Resistance, Junction-to-Ambient
(Note 1)
Junction and Storage Temperature
Range
Symbol
P
D
R
qJA
Max
357
2.9
350
Unit
mW
mW/°C
°C/W
xx = Device Code
(Refer to page 2)
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
NSBA1xxxDXV6T1
Package
Shipping
SOT−563* 4000/Tape & Reel
NSBA1xxxDXV6T1G SOT−563* 4000/Tape & Reel
Symbol
P
D
R
qJA
T
J
, T
stg
Max
500
4.0
250
−55 to
+150
Unit
mW
mW/°C
°C/W
°C
NSBA1xxxDXV6T5
SOT−563* 8000/Tape & Reel
NSBA1xxxDXV6T5G SOT−563* 8000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
**This
package is inherently Pb−Free.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. FR−4 @ Minimum Pad
DEVICE MARKING INFORMATION
See specific marking information in the device marking table
on page 2 of this data sheet.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
April, 2006 − Rev. 6
Publication Order Number:
NSBA114EDXV6/D

 
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