74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs
April 2007
74ACQ373, 74ACTQ373
Quiet Series™ Octal Transparent Latch with 3-STATE
Outputs
Features
■
I
CC
and I
OZ
reduced by 50%
■
Guaranteed simultaneous switching noise level and
■
■
■
■
■
■
tm
General Description
The ACQ/ACTQ373 consists of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfy-
ing the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in the HIGH
impedance state.
The ACQ/ACTQ373 utilizes Fairchild Quiet Series™
technology to guarantee quiet output switching and
improve dynamic threshold performance. features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
dynamic threshold performance
Guaranteed pin-to-pin skew AC performance
Improved latch up immunity
Eight latches in a single package
3-STATE outputs drive bus lines or buffer memory
address registers
Outputs source/sink 24mA
Faster prop delays than the standard AC/ACT373
Ordering Information
Order
Number
74ACQ373SC
74ACQ373SJ
74ACTQ373SC
74ACTQ373SJ
74ACQT373QSC
Package
Number
M20B
M20D
M20B
M20D
MQA20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
Description
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1989 Fairchild Semiconductor Corporation
74ACQ373, 74ACTQ373 Rev. 1.3
www.fairchildsemi.com
74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs
Logic Symbol
Functional Description
The ACQ/ACTQ373 contains eight D-type latches with
3-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes.
When LE is LOW, the latches store the information that
was present on the D inputs at setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the
2-state mode. When OE is HIGH, the standard outputs
are in the high impedance mode but this does not inter-
fere with entering new data into the latches.
IEEE/IEC
Truth Table
Inputs
LE
X
H
H
L
Outputs
D
n
X
L
H
X
OE
H
L
L
L
O
n
Z
L
H
O
0
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of
Latch Enable
©1989 Fairchild Semiconductor Corporation
74ACQ373, 74ACTQ373 Rev. 1.3
www.fairchildsemi.com
2
74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1989 Fairchild Semiconductor Corporation
74ACQ373, 74ACTQ373 Rev. 1.3
www.fairchildsemi.com
3
74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
V
CC
I
IK
Supply Voltage
DC Input Diode Current
V
I
=
–0.5V
V
I
=
V
CC
+ 0.5V
V
I
I
OK
DC Input Voltage
DC Output Diode Current
V
O
=
–0.5V
V
O
=
V
CC
+ 0.5V
V
O
I
O
DC Output Voltage
Parameter
Rating
–0.5V to +7.0V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
–20mA
+20mA
–0.5V to V
CC
+ 0.5V
±50mA
±50mA
–65°C to +150°C
±300mA
140°C
DC Output Source or Sink Current
I
CC
or I
GND
DC V
CC
or Ground Current per Output Pin
T
STG
Storage Temperature
DC Latch-Up Source or Sink Current
T
J
Junction Temperature
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
V
CC
Supply Voltage
ACQ
ACTQ
V
I
V
O
T
A
∆
V /
∆
t
∆V
/
∆
t
Input Voltage
Output Voltage
Operating Temperature
Parameter
Rating
2.0V to 6.0V
4.5V to 5.5V
0V to V
CC
0V to V
CC
–40°C to +85°C
125mV/ns
125mV/ns
Minimum Input Edge Rate, ACQ Devices:
V
IN
from 30% to 70% of V
CC
, V
CC
@ 3.0V, 4.5V, 5.5V
Minimum Input Edge Rate, ACTQ Devices:
V
IN
from 0.8V to 2.0V, V
CC
@ 4.5V, 5.5V
©1989 Fairchild Semiconductor Corporation
74ACQ373, 74ACTQ373 Rev. 1.3
www.fairchildsemi.com
4
74ACQ373, 74ACTQ373 Quiet Series™ Octal Transparent Latch with 3-STATE Outputs
DC Electrical Characteristics for ACQ
T
A
=
+25°C T
A
=
–40°C to +85°C
Symbol
V
IH
Parameter
Minimum HIGH Level
Input Voltage
V
CC
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Conditions
V
OUT
=
0.1V or
V
CC
– 0.1V
V
OUT
=
0.1V or
V
CC
– 0.1V
I
OUT
=
–50µA
Typ.
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
2.1
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
–75
4.0
±0.25
40.0
±2.5
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
Units
V
V
IL
Maximum LOW Level
Input Voltage
V
V
OH
Minimum HIGH Level
Output Voltage
V
V
IN
=
V
IL
or V
IH
:
3.0
4.5
5.5
V
OL
Maximum LOW Level
Output Voltage
3.0
4.5
5.5
V
IN
=
V
IL
or V
IH
3.0
4.5
5.5
I
IN(3)
I
OLD
I
OHD
I
CC(3)
I
OZ
Maximum Input Leakage
Current
Minimum Dynamic
Output Current
(2)
Maximum Quiescent
Supply Current
Maximum 3-STATE
Leakage Current
Quiet Output Maximum
Dynamic V
OL
Quiet Output Maximum
Dynamic V
OL
Minimum HIGH Level
Dynamic Input Voltage
Maximum LOW Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
I
OL
=
12 mA
I
OL
=
24 mA
I
OL
=
24 mA
(1)
V
I
=
V
CC
, GND
V
OLD
=
1.65V Max.
V
OHD
=
3.85V Min.
V
IN
=
V
CC
or GND
V
I
(OE)
=
V
IL
, V
IH
;
V
I
=
V
CC
, GND;
V
O
=
V
CC
, GND
Figures 1 & 2
(4)
Figures 1 & 2
(4)
(5)
I
OH
=
–12mA
I
OH
=
–24mA
I
OH
=
–24mA
(1)
I
OUT
=
50µA
0.002
0.001
0.001
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
V
µA
mA
mA
µA
µA
V
OLP
V
OLV
V
IHD
V
ILD
5.0
5.0
5.0
5.0
1.1
–0.6
3.1
1.9
1.5
–1.2
3.5
1.5
V
V
V
V
(5)
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
4. Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
5. Max number of data inputs (n) switching. (n–1) inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (V
ILD
), 0V to threshold (V
IHD
), f
=
1MHz.
©1989 Fairchild Semiconductor Corporation
74ACQ373, 74ACTQ373 Rev. 1.3
www.fairchildsemi.com
5
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