CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
Rev. 02 — 8 February 2007
Product data sheet
1. General description
The CBT3253A is a dual 1-of-4 high-speed TTL-compatible FET
multiplexer/demultiplexer. The low on-resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or generating additional ground
bounce noise.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
The CBT3253A is characterized for operation from
−40 °C
to +85
°C.
2. Features
5
Ω
switch connection between two ports
TTL-compatible input levels
Minimal propagation delay through the switch
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
I
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I
I
I
I
3. Ordering information
Table 1.
Ordering information
T
amb
=
−
40
°
C to +85
°
C
Type number
CBT3253AD
Topside
mark
CBT3253AD
Package
Name
SO16
SSOP16
SSOP16
[1]
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package;
16 leads; body width 5.3 mm
plastic shrink small outline package;
16 leads; body width 3.9 mm;
lead pitch 0.635 mm
Version
SOT109-1
SOT338-1
SOT519-1
CBT3253ADB C3253A
CBT3253ADS CT3253A
CBT3253APW CT3253A
[1]
Also known as QSOP16.
TSSOP16
plastic thin shrink small outline package; SOT403-1
16 leads; body width 4.4 mm
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
4. Functional diagram
CBT3253A
1A
7
6
5
4
3
9
10
11
12
13
1B1
1B2
1B3
1B4
2B1
2B2
2B3
2B4
2A
S0
14
S1
2
1OE
1
2OE
15
002aab828
Fig 1. Logic diagram of CBT3253A (positive logic)
CBT3253A_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 8 February 2007
2 of 17
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
5. Pinning information
5.1 Pinning
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
16 V
CC
15 2OE
14 S0
13 2B4
1OE
S1
1B4
1B3
1B2
1B1
1
2
3
4
5
6
7
8
002aab825
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
CBT3253AD
5
6
7
8
002aab824
12 2B3
11 2B2
10 2B1
9
2A
CBT3253ADB
1A
GND
Fig 2. Pin configuration for SO16
Fig 3. Pin configuration for SSOP16
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
5
6
7
8
002aab826
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
1
2
3
4
5
6
7
8
002aab827
16 V
CC
15 2OE
14 S0
13 2B4
12 2B3
11 2B2
10 2B1
9
2A
CBT3253ADS
CBT3253APW
Fig 4. Pin configuration for SSOP16
(QSOP16)
Fig 5. Pin configuration for TSSOP16
5.2 Pin description
Table 2.
Symbol
1OE
S1
1B4, 1B3, 1B2, 1B1
1A
GND
2A
2B1, 2B2, 2B3, 2B4
S0
2OE
V
CC
[1]
CBT3253A_2
Pin description
Pin
1
2
3, 4, 5, 6
7
8
9
10, 11, 12, 13
14
15
16
Description
output enable (active LOW)
select-control input
B outputs
[1]
A input
ground (0 V)
A input
B outputs
select-control input
output enable (active LOW)
positive supply voltage
B outputs are inputs if A inputs are outputs.
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 8 February 2007
3 of 17
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
6. Functional description
Refer to
Figure 1 “Logic diagram of CBT3253A (positive logic)”
6.1 Function selection
Table 3.
Function selection
H = HIGH state; L = LOW state; X = Don’t Care
Inputs
1OE
X
H
L
L
L
L
2OE
H
X
L
L
L
L
S1
X
X
L
L
H
H
S0
X
X
L
H
L
H
disconnect 1A and 2A
disconnect 1A and 2A
1A to 1B1 and 2A to 2B1
1A to 1B2 and 2A to 2B2
1A to 1B3 and 2A to 2B3
1A to 1B4 and 2A to 2B4
Function
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
I
CCC
I
IK
T
stg
[1]
Parameter
supply voltage
input voltage
continuous current through
each V
CC
or GND pin
input clamping current
storage temperature
Conditions
Min
−0.5
−0.5
[1]
-
Max
+7.0
+7.0
128
−50
+150
Unit
V
V
mA
mA
°C
V
I
< 0 V
-
−65
The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings
are observed.
8. Recommended operating conditions
Table 5.
Operating conditions
All unused control inputs of the device must be held at V
CC
or GND to ensure proper device
operation.
Symbol
V
CC
V
IH
V
IL
T
amb
Parameter
supply voltage
HIGH-level input voltage
LOW-level input voltage
ambient temperature
operating in free air
Conditions
Min
4.5
2
-
−40
Typ
-
-
-
-
Max
5.5
-
0.8
+85
Unit
V
V
V
°C
CBT3253A_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 8 February 2007
4 of 17
NXP Semiconductors
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
9. Static characteristics
Table 6.
Static characteristics
T
amb
=
−
40
°
C to +85
°
C
Symbol
V
IK
V
pass
I
LI
I
CC
∆I
CC
C
i
C
io(off)
C
io(on)
R
on
Parameter
input clamping voltage
pass voltage
input leakage current
quiescent supply current
additional quiescent supply
current (control inputs)
input capacitance
(control pins)
off-state input/output
capacitance
on-state input/output
capacitance
ON-state resistance
[3]
Conditions
V
CC
= 4.5 V; I
I
=
−18
mA
V
I
= V
CC
= 5.5 V; I
O
=
−100 µA
V
CC
= 5 V; V
I
= 5.5 V or GND
V
CC
= 5.5 V; I
O
= 0 mA;
V
I
= V
CC
or GND
V
CC
= 5.5 V; one input at 3.4 V;
other inputs at V
CC
or GND
V
I
= 3 V or 0 V
A port; V
O
= 3 V or 0 V; OE = V
CC
B port; V
O
= 3 V or 0 V; OE = V
CC
A port and B port
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 64 mA
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 30 mA
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
=
−15
mA
[1]
[2]
[3]
All typical values are at V
CC
= 5 V, T
amb
= 25
°C.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
[2]
Min
-
3.4
-
-
-
-
-
-
-
-
-
-
Typ
[1]
-
3.6
-
-
-
4.5
11.4
3.8
18.6
5
5
10
Max
−1.2
3.9
±1
3
2.5
-
-
-
-
7
7
15
Unit
V
V
µA
µA
mA
pF
pF
pF
pF
Ω
Ω
Ω
10. Dynamic characteristics
Table 7.
Dynamic characteristics
V
CC
= +5.0 V
±
0.5 V; T
amb
=
−
40
°
C to +85
°
C; unless otherwise specified.
Symbol
t
PD
t
en
t
dis
Parameter
propagation delay
enable time
[2]
disable time
[3]
Conditions
from input (nA or nBn) to output (nBn or nA)
from input (Sn) to output (nA or nBn)
from input (Sn) to output (nA or nBn)
from input (nOE) to output (nA or nBn)
from input (Sn) to output (nA or nBn)
from input (nOE) to output (nA or nBn)
[1]
[2]
[3]
[1]
Min
-
1.2
1.3
1.4
1.1
1.0
Typ
-
-
-
-
-
-
Max
0.25
6.2
6.3
6.4
7.2
7
Unit
ns
ns
ns
ns
ns
ns
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
Output enable time to HIGH and LOW level.
Output disable time from HIGH and LOW level.
CBT3253A_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 8 February 2007
5 of 17
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
