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LAN91C96QFP: 产品描述以太网 IC non-pci 10 mbps ethernet mac; 产品类别半导体其他集成电路（IC）; 文件大小655KB，共125页; 制造商All Sensors

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LAN91C96QFP概述

以太网 IC non-pci 10 mbps ethernet mac

LAN91C96QFP规格参数

参数名称	属性值
厂商名称	All Sensors
产品种类	以太网 IC
RoHS	否
产品	Ethernet Controllers
收发器数量	1
支持标准	802.3, 802.3u
数据速率	10 MB, 100 MB
电源电压（最大值）	5 V
电源电压（最小值）	0 V
电源电流（最大值）	95 mA
最大工作温度	+ 70 C
封装 / 箱体	TQFP-100
封装	Bulk
以太网连接类型	10 Base-T, 100 Base-TX
最小工作温度	0 C
安装风格	SMD/SMT
类型	Single Chip MAC and PHY Controlle

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LAN91C96

Non-PCI Single-Chip

Full Duplex Ethernet

Controller with Magic

Packet

Datasheet

Product Features

Non-PCI Single-Chip Ethernet Controller

A Subset of Motorola 68000 Bus Interface

Support

Fully Supports Full Duplex Switched Ethernet

Supports Enhanced Transmit Queue

Management

6K Bytes of On-Chip RAM

Supports IEEE 802.3 (ANSI 8802-3) Ethernet

Standards

Automatic Detection of TX/RX Polarity Reversal

Enhanced Power Management Features

Supports “Magic Packet” Power Management

Technology

Hardware Memory Management Unit

Optional Configuration via Serial EEPROM

Interface (Jumperless)

Supports single +5V or +3.3V (for Revisions E

and Later) VCC Designs

Supports Mixed Voltage External PHY Designs

Low Power CMOS Design

100 Pin QFP and TQFP (1.0 mm body

Thickness) Lead-Free RoHS Compliant

Packages

Pin Compatible with the LAN91C92 and

LAN91C94

Bus Interface

Direct Interface to Local Bus, PCMCIA, and

68000 Buses with No Wait States

Flexible Bus Interface

16 Bit Data and Control Paths

Fast Access Time

Pipelined Data Path

Handles Block Word Transfers for any

Alignment

High Performance Chained ("Back-to-Back")

Transmit and Receive

Pin Compatible with the LAN91C92 (in Local

Bus Mode) and the LAN91C94 in Both Local

Bus and PCMCIA Modes

Dynamic Memory Allocation Between Transmit

and Receive

Flat Memory Structure for Low CPU Overhead

Buffered Architecture, Insensitive to Bus

Latencies (No Overruns/Underruns)

Supports Boot PROM for Diskless Local Bus

Applications

Network Interface

Integrated 10BASE-T Transceiver Functions:

Driver and Receiver

Link Integrity Test

Receive Polarity Detection and Correction

Integrated AUI Interface

10 Mb/s Manchester Encoding/Decoding and

Clock Recovery

Automatic Retransmission, Bad Packet

Rejection, and Transmit Padding

External and Internal Loopback Modes

Four Direct Driven LEDs for Status/ Diagnostics

Software Drivers

LAN9000 Drivers for Major Network Operating

Systems Utilizing Local Bus or PCMCIA

Interface

Software Drivers Compatible with the

LAN91C92, LAN91C94, LAN91C100FD (100

Mb/s), and LAN91C110 (100 Mb/s) Controllers

in Local Bus Mode

Software Drivers Utilize Full Capability of 32 Bit

Microprocessor

Refer to Description of Pin Functions on Page 17 for

5V tolerant pins

SMSC LAN91C96 5v&3v

Revision 1.0 (10-24-08)

DATASHEET

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

Datasheet

ORDER NUMBERS:

LAN91C96-MS for 100 pin, QFP Lead-Free RoHS Compliant package

LAN91C96-MU for 100 pin, TQFP Lead-Free RoHS Compliant package

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete

information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no

responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without

notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does

not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC

or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard

Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors

known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request.

SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause

or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further

testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale

Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems

Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND

ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY

DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR

REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC

OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO

HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH

DAMAGES.

Revision 1.0 (10-24-08)

Page 2

SMSC LAN91C96 5v&3v

DATASHEET

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

Datasheet

Table of Contents

CHAPTER 1 GENERAL DESCRIPTION ..................................................................... 7

CHAPTER 2 OVERVIEW ............................................................................................. 8

CHAPTER 3 PIN CONFIGURATIONS....................................................................... 11

3.1

Local Bus vs. PCMCIA vs. 68000 Pin Requirements...................................................................................15

CHAPTER 4 DESCRIPTION OF PIN FUNCTIONS ................................................... 17

4.1

Buffer Symbols................................................................................................................................................21

CHAPTER 5 FUNCTIONAL DESCRIPTION .............................................................. 23

5.1

5.2

5.3

5.4

5.5

5.6

Buffer Memory................................................................................................................................................24

Interrupt Structure.........................................................................................................................................31

Reset Logic.......................................................................................................................................................32

Power Down Logic States...............................................................................................................................32

LAN91C96 Power Down States .....................................................................................................................33

PCMCIA CONFIGURATION REGISTERS DESCRIPTION ..................................................................36

CHAPTER 6 FRAME FORMAT IN BUFFER MEMORY FOR ETHERNET ............... 38

CHAPTER 7 REGISTERS MAP IN I/O SPACE ......................................................... 42

7.1

7.2

I/O Space Access .............................................................................................................................................42

I/O Space Registers Description ....................................................................................................................42

CHAPTER 8 THEORY OF OPERATION ................................................................... 65

8.1

8.2

8.3

Typical Flow of Events for Transmit (Auto Release = 0) ............................................................................67

Typical Flow of Events for Transmit (Auto Release = 1) ............................................................................68

Flow of Events for Receive .............................................................................................................................69

CHAPTER 9 FUNCTIONAL DESCRIPTION OF THE BLOCKS................................ 79

SMSC LAN91C96 5v&3v

Page 3

Revision 1.0 (10-24-08)

DATASHEET

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

Datasheet

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

9.10

9.11

9.12

Memory Management Unit ............................................................................................................................79

Arbiter .............................................................................................................................................................79

Bus Interface ...................................................................................................................................................80

Wait State Policy .............................................................................................................................................80

Arbitration Considerations ............................................................................................................................81

DMA Block ......................................................................................................................................................82

Packet Number FIFOS ...................................................................................................................................82

CSMA Block....................................................................................................................................................84

Network Interface ...........................................................................................................................................85

10Base-T.......................................................................................................................................................86

AUI ...............................................................................................................................................................86

Physical Interface ........................................................................................................................................86

9.13

Transmit Functions .....................................................................................................................................86

9.13.1

Manchester Encoding.............................................................................................................................86

9.13.2

Transmit Drivers ....................................................................................................................................86

9.13.3

Jabber Function ......................................................................................................................................87

9.13.4

SQE Function.........................................................................................................................................87

9.14

Receive Functions........................................................................................................................................87

9.14.1

Receive Drivers......................................................................................................................................87

9.14.2

Manchester Decoder and Clock Recovery .............................................................................................87

9.14.3

Squelch Function....................................................................................................................................87

9.14.4

Reverse Polarity Function ......................................................................................................................87

9.14.5

Collision Detection Function .................................................................................................................88

9.14.6

Link Integrity .........................................................................................................................................88

CHAPTER 10

10.1

10.2

10.3

BOARD SETUP INFORMATION ........................................................ 89

Diagnostic LEDs ..........................................................................................................................................90

Bus Clock Considerations...........................................................................................................................90

68000 Bus Interface.....................................................................................................................................90

CHAPTER 11

11.1

11.2

OPERATIONAL DESCRIPTION ......................................................... 92

Maximum Guaranteed Ratings* ................................................................................................................92

DC Electrical Characteristics.....................................................................................................................92

Revision 1.0 (10-24-08)

Page 4

SMSC LAN91C96 5v&3v

DATASHEET

Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet

Datasheet

CHAPTER 12

CHAPTER 13

TIMING DIAGRAMS ........................................................................... 99

LAN91C96 REVISIONS .................................................................... 125

List of Figures

Figure 3.1 - LAN91C96 100 Pin QFP...........................................................................................................................11

Figure 3.2 - LAN91C96 100 Pin TQFP.........................................................................................................................12

Figure 3.3 - LAN91C96 System Block Diagram ...........................................................................................................13

Figure 3.4 – System Diagram for Local Bus with Boot Prom .......................................................................................14

Figure 4.1 - LAN91C96 Internal Block Diagram ...........................................................................................................22

Figure 5.1 – Mapping and Paging vs. Receive and Transmit Area ..............................................................................25

Figure 5.2 – Transmit Queues and Mapping................................................................................................................26

Figure 5.3 – Receive Queues and Mapping.................................................................................................................27

Figure 5.4 - LAN91C96 Internal Block Diagram with Data Path...................................................................................28

Figure 5.5 – Logical Address Generation and Relevant Registers...............................................................................29

Figure 6.1 – Data Frame Format..................................................................................................................................38

Figure 6.2 - LAN91C96 Registers ................................................................................................................................41

Figure 7.1 – Interrupt Structure.....................................................................................................................................61

Figure 8.1 – Interrupt Service Routine .........................................................................................................................70

Figure 8.2 - RX INTR ...................................................................................................................................................71

Figure 8.3 -TX INTR.....................................................................................................................................................72

Figure 8.4 -TXEMPTY INTR ........................................................................................................................................73

Figure 8.5 – Driver Send and Allocate Routines ..........................................................................................................74

Figure 8.6 – Interrupt Generation for Transmit; Receive, MMU ...................................................................................78

FIGURE 9.1 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS.........................................................84

FIGURE 10.1 - 64 X 16 SERIAL EEPROM MAP .........................................................................................................91

Figure 12.1 – Card Configuration Registers – Read/Write PCMCIA Mode (A15=1) ....................................................99

Figure 12.2 – Local Bus Consecutive Read Cycles ...................................................................................................100

Figure 12.3 - PCMCIA Consecutive Read Cycles ......................................................................................................101

Figure 12.4 – Local Bus Consecutive Write Cycles....................................................................................................102

Figure 12.5 - PCMCIA Consecutive Write Cycles ......................................................................................................103

Figure 12.6 – Local Bus Consecutive Read and Write Cycles ...................................................................................104

Figure 12.7 – Data Register Special Read Access ....................................................................................................105

Figure 12.8 – Data Register Special Write Access.....................................................................................................106

Figure 12.9 - 8-Bit Mode Register Cycles ..................................................................................................................107

Figure 12.10 - 68000 Read Timing.............................................................................................................................108

Figure 12.11 - 68000 Write Timing.............................................................................................................................109

Figure 12.12 – External ROM Read Access ..............................................................................................................110

Figure 12.13 – Local Bus Register Access When Using Bale ....................................................................................111

Figure 12.14 – External ROM Read Access Using Bale ............................................................................................112

Figure 12.15 - EEPROM Read...................................................................................................................................113

Figure 12.16 - EEPROM Write ...................................................................................................................................114

Figure 12.17 - PCMCIA Attribute Memory Read/Write (A15=0) .................................................................................115

Figure 12.18 – External ENDEC Interface – Start of Transmit ...................................................................................115

Figure 12.19 – External ENDEC Interface – Receive Data ........................................................................................116

Figure 12.20 – Differential Output Signal Timing (10BASE-T and AUI) .....................................................................117

Figure 12.21 – Receive Timing – Start of Frame (AUI and 10BASE-T) .....................................................................118

Figure 12.22 – Receive Timing – End of Frame (AUI and 10BASE-T).......................................................................119

Figure 12.23 – Transmit Timing – End of Frame (AUI and 10BASE-T)......................................................................120

Figure 12.24 – Collision Timing (AUI) ........................................................................................................................121

Figure 12.25 – Memory Read Timing.........................................................................................................................121

Figure 12.26 – Input Clock Timing .............................................................................................................................122

Figure 12.27 – Memory Write Timing .........................................................................................................................122

Figure 12.28 - 100 PIN QFP Package........................................................................................................................123

Figure 12.29 - 100 PIN TQFP Package .....................................................................................................................124

SMSC LAN91C96 5v&3v

Page 5

Revision 1.0 (10-24-08)

DATASHEET

LAN91C96QFP相似产品对比

	LAN91C96QFP	LAN91C96ITQFP	LAN91C96-MU
描述	以太网 IC non-pci 10 mbps ethernet mac	以太网 IC non-pci 10 mbps ethernet mac	以太网 IC ethernet IC 10mbps mac phy
厂商名称	All Sensors	All Sensors	All Sensors
产品种类	以太网 IC	以太网 IC	以太网 IC
RoHS	否	否	是
产品	Ethernet Controllers	Ethernet Controllers	Ethernet Controllers
收发器数量	1	1	1
支持标准	802.3, 802.3u	802.3, 802.3u	802.3, 802.3u
数据速率	10 MB, 100 MB	10 MB, 100 MB	10 MB, 100 MB
电源电压（最大值）	5 V	5 V	5 V
电源电压（最小值）	0 V	0 V	0 V
电源电流（最大值）	95 mA	95 mA	95 mA
最大工作温度	+ 70 C	+ 70 C	+ 70 C
封装 / 箱体	TQFP-100	TQFP-100	TQFP-100
以太网连接类型	10 Base-T, 100 Base-TX	10 Base-T, 100 Base-TX	10 Base-T, 100 Base-TX
最小工作温度	0 C	0 C	0 C
安装风格	SMD/SMT	SMD/SMT	SMD/SMT
类型	Single Chip MAC and PHY Controlle	Single Chip MAC and PHY Controlle	Single Chip MAC and PHY Controlle

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器件捷径: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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