Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
1
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
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General Description
Pin Configuration
N/C
P
GND
GND
Mode
P
IN
N
IN
EN
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
The Supertex HV450 is a PWM high voltage ring generator. The
high voltage output P- and N-channel transistors are controlled
independently by the logic inputs P
IN
and N
IN
. For application
where a single control pin (N
IN
) is desired, the mode pin should
be connected to Gnd. This adds a 200ns deadband on the
control logic to avoid cross conduction on the high voltage
output. A logic high on N
IN
will turn the high voltage P-Channel on
and the N-Channel off. The outputs can drive up to 5 RENs. The
HV450 can drive external MOSFETs for applications requiring
larger loads. The IC can be powered down by connecting the
enable pin to V
DD
. The high voltage outputs have pulse by pulse
over current protection.
V
PP
P
GATE
V
PSEN
HV
OUT
V
NSEN
N
GATE
V
NN2
V
NN1
top view
SOW-16
HV450
Electrical Characteristics
(Over operating supply voltages unless otherwise specified, T
A
= -40°C to +85°C.)
Symbol Parameters
V
PP
V
NN1
V
NN2
V
DD
I
NN1Q
I
DDQ
I
NN1
I
DD
I
IL
V
IL
V
IH
P-channel linear regulator output voltage
Min
-10
- 220
4.5
Typ
Max
-18
-110
V
NN1
+ 10.0
5.5
Unit
V
V
V
V
µA
µA
mA
Conditions
High voltage negative supply
Logic supply voltage
V
NN1
quiescent current
V
DD1
quiescent current
V
NN1
operating current
V
DD
operating current
Mode logic input low current
Logic input low voltage
Logic input high voltage
Negative linear regulator output voltage V
NN1
+ 6.0
300
90
35
1.4
500
25
200
100
P
IN
= N
IN
= EN = L
P
IN
= N
IN
= L, EN = H
P
IN
= N
IN
= EN = L
P
IN
= N
IN
= L, EN = H
No load, V
OUTP
and V
OUTN
switching at
100KHz
Mode = 0V
V
DD
= 5.0V
V
DD
= 5.0V
1.0
25
0
4.0
1.0
5.0
mA
µA
V
V
High Voltage Output
Symbol Parameters
R
SOURCE
V
OUT
P source resistance
R
SINK
t
d(ON)
t
rise
t
d(OFF)
t
fall
t
db
V
psen
V
nsen
t
shortP
t
shortN
t
whout
t
wlout
V
OUT
P sink resistance
HV
OUT
delay time
HV
OUT
rise time
HV
OUT
delay time
HV
OUT
fall time
Logic deadband time
HV
OUT
current source sense voltage
HV
OUT
current sink sense voltage
HV
OUT
off delay time when current
source sense is activiated
HV
OUT
off delay time when current sink
sense is activated
Minimum pulse width for HV
OUT
at P
GND
Minimum pulse width for HV
OUT
at V
NN1
-1.2
V
NN1
+ 0.8
70
70
Min
Typ
65
65
150
50
200
50
250
-0.8
V
NN1
+ 1.2
150
150
500
500
Max
Unit
Ω
Ω
ns
ns
ns
ns
ns
V
V
ns
ns
ns
ns
Conditions
I
OUT
= 100mA
I
OUT
= -100mA
P
IN
= high to low, Mode = high
P
IN
= high to low
N
IN
= low to high, Mode = high
N
IN
= low to high
Mode = low
Truth Table
N
IN
L
L
H*
H
L
H
X
P
IN
L
H
L*
H
X
X
X
Mode
H
H
H
H
L
L
X
EN
L
L
L
L
L
L
H
HV
OUT
Pgnd
High Z
*
V
NN1
V
NN1
Pgnd
High Z
*This state will short V
NN1
to Pgnd and should therefore be avoided.
2
HV450
Block Diagram
P
GND
Current
Sense
and
Driver
Linear
Reg
V
psen
V
DD
P
IN
N
IN
EN
Mode
GND
High
Voltage
Level
Translator
P
gate
V
PP
HV
OUT
Logic
V
DD
High
Voltage
Level
Translator
Linear
Reg
V
NN2
N
gate
Current
Sense
and
Driver
V
nsen
V
NN1
Pin Description
V
PP
V
NN1
V
NN2
V
DD
GND
P
GND
P
IN
N
IN
EN
Mode
HV
OUT
V
psen
V
nsen
P
gate
N
gate
P-channel gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between
P
GND
and V
PP
.
Negative high voltage supply.
N-channel gate voltage supply. Generated by an internal linear regulator. A 0.1µF capacitor should be connected between
V
NN2
and V
NN1
.
Logic supply voltage.
Low voltage ground.
High voltage power ground.
Logic control input. When mode is high, logic input high turns OFF output high voltage P-Channel.
Logic control input. When mode is high, logic input high turns ON output high voltage N-Channel.
Logic enable input. Logic low enables IC.
Logic mode input. Logic low activates 200nsec deadband. When mode is low, N
IN
turns on and off the high voltage N- and
P-Channels. Pin is not used and should be connected to V
DD
or ground.
High voltage output. Voltage swings from P
GND
to V
NN1
.
Pulse by pulse over current sensing for P-Channel MOSFET.
Pulse by pulse over current sensing for N-Channel MOSFET.
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