Si5022-EVB
Functional Description
The evaluation board simplifies characterization of the
Si5022 Clock and Data Recovery (CDR) device by
providing access to all of the Si5022 I/Os. Device
performance can be evaluated by following the “Test
Configuration” section. Specific performance metrics
include input sensitivity, jitter tolerance, jitter generation,
and jitter transfer.
When applied, REFCLK is used to center the frequency
of the DSPLL™ so that the device can lock to the data.
Ideally, the REFCLK frequency should be 1/128th,
1/32nd, or 1/16th the VCO frequency and must have a
frequency accuracy of ±100 ppm. Internally, the CDR
automatically recognizes the REFCLK frequency within
one of these three frequency ranges. Typical REFCLK
frequencies are given in Table 1. REFCLK is ac coupled
to the SMA jacks located on the top side of the
evaluation board.
Power Supply
The evaluation board requires one 2.5 V supply. Supply
filtering is placed on the board to filter typical system
noise components; however, initial performance testing
should use a linear supply capable of supplying the
nominal voltage ±5% dc.
CAUTION:
The evaluation board is designed so that the
body of the SMA jacks and GND are shorted. Care must
be taken when powering the PCB at potentials other
than GND at 0.0 V and VDD at 2.5 V relative to chassis
GND.
Table 1. Typical REFCLK Frequencies
SONET/SDH
19.44 MHz
77.76 MHz
155.52 MHz
Gigabit
Ethernet
19.53 MHz
78.125 MHz
156.25 MHz
SONET/SDH
with
15/14 FEC
20.83 MHz
83.31 MHz
166.63 MHz
Ratio of
VCO to
REFCLK
128
32
16
Device Powerdown
The CDR can be powered down via the RESET/CAL
signal. When asserted, the evaluation board will draw
minimal current. RESET/CAL is controlled via one
jumper located in the lower left-hand corner of the
evaluation board. RESET/CAL is wired to the signal
post adjacent to the VDD post. For a valid reset to occur
when using external reference clock mode, a proper
external reference clock frequency must be applied as
specified in Table 1. CLKOUT, DATAOUT, DATAIN
CLKOUT, DATAOUT, and DATAIN (all high-speed I/Os)
are wired to the board perimeter on 30 mil (0.030 inch)
50
Ω
microstrip lines to the end-launch SMA jacks as
labeled on the PCB. These I/Os are ac coupled to
simplify direct connection to a wide array of standard
test hardware. Because each of these signals are
differential, both the positive (+) and negative (–)
terminals must be terminated to 50
Ω.
Terminating only
one side will adversely degrade the performance of the
CDR. The inputs are terminated on the die with 50
Ω
resistors.
Note:
The 50
Ω
termination is for each terminal/side of a dif-
ferential signal, thus the differential termination is actu-
ally 50
Ω
+ 50
Ω
= 100
Ω.
RATESEL
RATESEL is used to configure the CDR to recover clock
and data at different data rates. RATESEL is a two bit
binary input controlled via two jumpers located in the
lower left-hand corner of the evaluation board.
RATESEL0/1 are wired to the center posts (signal post)
between VDD and GND. For example, the OC-48 data
rate is selected by jumping RATESEL0 to 1 and
RATESEL1 to 1.
GND
GND
RATESEL1
RATESEL0
622 Mbps
GND
RATESEL1
RATESEL0
155 Mbps
VDD
RATESEL1
RATESEL0
1244 Mbps
VDD
VDD
RATESEL1
RATESEL0
2488 Mbps
GND
VDD
Figure 1. RATESEL Jumper Configurations
REFCLK
REFCLK is optional for clock and data recovery within
the Si5022 device. If REFCLK is not used, jumper both
JP15 and JP16. These jumpers pull the REFCLK+ input
to VDD and REFCLK– input to GND, which configures
the device to operate without an external reference.
Loss-of-Lock (LOL)
Loss-of-lock (LOL) is an indicator of the relative
frequency between the data and the REFCLK. LOL will
assert when the frequency difference is greater than
±600 ppm. In order to prevent LOL from de-asserting
2
Rev. 1.0
Si5022-EVB
prematurely, there is hysterisis in returning from the out-
of-lock condition. LOL will be de-asserted when the
frequency difference is less than ±300 ppm.
LOL is wired to a test point which is located on the
upper right-hand side of the evaluation board.
“BER Detection” section of the Si5022/Si5023 data
sheet for threshold level programming. The BER_MON
signal (JP14) is reserved for factory testing purposes.
Test Configuration
The three critical jitter tests typically performed on a
CDR device are jitter transfer, jitter tolerance, and jitter
generation. By connecting the Si5022 Evaluation Board
as shown in Figure 3, all three measurements can be
easily made.
When applied, REFCLK should be within ±100 PM of
the frequency selected from Table 1. RATESEL must be
configured to match the desired data rate, and
PWRDN/CAL must be unjumpered.
Jitter Tolerance:
Referring to Figure 3, this test
requires a pattern generator, a clock source
(synthesizer signal source), a modulation source, a jitter
analyzer, a pattern analyzer, and a pulse generator (all
unconnected high-speed outputs must be terminated to
50
Ω).
During this test, the Jitter Analyzer directs the
Modulation Source to apply prescribed amounts of jitter
to the synthesizer source. This “jitters” the pattern
generator timebase which drives the DATAIN ports of
the CDR. The Bit-Error-Rate (BER) is monitored on the
Pattern Analyzer. The modulation (jitter) frequency and
amplitude is recorded when the BER approaches a
specified threshold. The Si5022 limiting amplifier can
also be examined during this test. Simply lower the
amplitude of the incoming data to the minimum value
typically expected at the limiting amplifier inputs
(typically 10 mV
PP
for the Si5022 device).
Jitter Generation:
Referring to Figure 3, this test
requires a pattern generator, a clock source
(synthesizer signal source), a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50
Ω).
During this test, there is no
modulation of the Data Clock, so the data that is sent to
the CDR is jitter free. The Jitter Analyzer measures the
RMS and peak-to-peak jitter on the CDR CLKOUT.
Thus, any jitter measured is jitter generated by the
CDR.
Jitter Transfer:
Referring to Figure 3, this test requires
a pattern generator, a clock source (synthesizer signal
source), a modulation source, a jitter analyzer, and a
pulse generator (all unconnected high-speed outputs
must be terminated to 50
Ω).
During this test, the Jitter
Analyzer modulates the data pattern and data clock
reference. The modulated data clock reference is
compared with the CLKOUT of the CDR. Jitter on
CLKOUT relative to the jitter on the data clock reference
is plotted versus modulation frequency at predefined
jitter amplitudes.
Loss-of-Signal Alarm Threshold Control
The loss-of-signal alarm (LOS) is used to signal low
incoming data amplitude levels. The input signal to the
threshold control is set by applying a dc voltage level to
the LOS_LVL pin. LOS_LVL is controllable through the
BNC jack J10. The mapping of the LOS_LVL voltage to
input signal alarm threshold level is shown in Figure 2. If
this function is not used, jumper JP1.
40 mV
LOS Threshold (mV
PP
)
30 mV
LOS Disabled
15 mV
LOS
Undefined
40 mV/V
0 mV
0V
1.00 V
1.50 V
1.875 V
2.25 V
2.5 V
LOS_LVL (V)
Figure 2. LOS_LVL Mapping
Data Slicing Level
The slicing level allows optimization of the input cross-
over point for systems where the slicing level is not at
the amplitude average. The data slicing level can be
adjusted from the nominal cross-over point of the data
by applying a voltage to the SLICE_LVL pin.
SLICE_LVL is controllable through the BNC jack J11.
The SLICE_LVL to the data slicing level is mapped as
follows:
V
SLICE_LVL
–
1.5
-
V
SLICE
= -------------------------------------------
50
If this function is not used, jumper JP6.
Bit-Error-Rate Alarm Threshold
The bit-error-rate of the incoming data can be monitored
by the BER_ALM pin. When the bit-error-rate exceeds
an externally set threshold level, BER_ALM is asserted.
BER_ALM is brought to a test point located in the upper
right-hand corner of the board. The BER_ALM threshold
level is set by applying a dc voltage to the BER_LVL pin.
BER_LVL is controllable through the BNC jack J12.
Jumper JP7 to disable the BER alarm. Refer to the
Rev. 1.0
3
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