PACVGA201
VGA Port Companion Circuit
Features
•
•
•
•
•
•
•
Seven channels of ESD protection for all VGA port
connector pins
Meets IEC-61000-4-2 Level-4 ESD requirements
(8kV contact discharge)
Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF typical
TTL to CMOS level-translating buffers with power
down mode for HSYNC and VSYNC lines
Three power supplies for design flexibility
Compact 16-pin QSOP package
RoHS compliant (lead-free) finishing
Product Description
The PACVGA201 provides seven channels of ESD pro-
tection for all signal lines commonly found in a VGA
port. ESD protection is implemented with current-steer-
ing diodes designed to safely handle the high surge
currents encountered with IEC-61000-4-2 Level-4 ESD
Protection (8kV contact discharge). When a channel is
subjected to an electrostatic discharge, the ESD cur-
rent pulse is diverted via the protection diodes into the
positive supply rail or ground where it may be safely
dissipated.
Separate positive supply rails are provided for the
VIDEO, DDC_OUT and SYNC channels to facilitate
interfacing with low-voltage video controller ICs and to
provide design flexibility in multiple-supply-voltage
environments.
An internal diode (D
1
, in schematic below) is provided
such that V
CC2
is derived from V
CC3
(V
CC2
does not
require an external power supply input). In applications
where V
CC3
may be powered down, diode D
1
blocks
any DC current path from the DDC_OUT pins back to
the powered down V
CC3
rail via the upper ESD protec-
tion diodes. (cont’d
next page)
Applications
•
•
•
•
ESD protection and termination resistors for VGA
(video) port interfaces
Desktop PCs
Notebook computers
LCD monitors
Simplified Electrical Schematic
V
CC1
2
V
CC2
8
V
CC3
D
1
1
15
VIDEO_1
VIDEO_2
VIDEO_3
3
4
5
R
B
SD1
16
SD2
GND
6
14
12
DDC_OUT1
DDC_OUT2
SYNC_IN1
SYNC_IN2
9
10
GND
R
P
SYNC_OUT2
SYNC_OUT1
PWR_UP
7
11
13
GND
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 04/24/08
●
Fax: 408.263.7846
●
www.cmd.com
1
PACVGA201
Product Description (cont’d)
Two non-inverting drivers provide buffering for the
HSYNC and VSYNC signals from the Video Controller
IC (SYNC_IN1, SYNC_IN2). These buffers accept TTL
input levels and convert them to CMOS output levels
that swing between Ground and V
CC3
.
When the PWR_UP input is driven LOW, the SYNC
outputs are driven LOW and the SYNC inputs can float:
no current will be drawn from the VCC3 supply.
The PACVGA201 is housed in a 16-pin QSOP package
with RoHS compliant lead-free finishing.
PACKAGE / PINOUT DIAGRAM
Top View
V
CC3
V
CC1
VIDEO_1
VIDEO_2
VIDEO_3
GND
PWR_UP
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SD2
SD1
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_OUT1
16-Pin QSOP
Note: This drawing is not to scale.
Ordering Information
PART NUMBERING INFORMATION
Pins
16
Package
QSOP
Ordering Part Number
1
PACVGA201QR
Part Marking
PACVGA 201QR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
© 2008 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 04/24/08
●
Fax: 408.263.7846
●
www.cmd.com
PACVGA201
Pin Description
PIN DESCRIPTIONS
Pins(s)
1
2
3
4
5
6
7
8
NAME
V
CC3
V
CC1
VIDEO_1
VIDEO_2
VIDEO_3
GND
PWR_UP
V
CC2
DESCRIPTION
V
CC3
supply pin. This is an isolated supply input for the two sync buffers and SD1 and SD2
ESD protection circuits.
V
CC1
supply pin. This is an isolated supply pin for the VIDEO_1, VIDEO_2 and VIDEO_3
ESD protection circuits.
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the VGA controller device and the video connector.
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the VGA controller device and the video connector.
Video signal ESD protection channel. This pin is typically tied one of the video lines between
the VGA controller device and the video connector.
Ground reference supply pin.
Enables the sync buffers when high. When PWR_UP is low the sync outputs are forced low
and the inputs can be floated.
V
CC2
supply pin. This is an isolated supply pin for the DDC_OUT1 and DDC_OUT2 ESD pro-
tection circuits. Internally, V
CC2
is derived from the V
CC3
input if the V
CC2
input is not con-
nected to a supply voltage.
DDC_OUT1 ESD protection channel.
DDC_OUT2 ESD protection channel
Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines.
Sync signal buffer output. Connects to the video connector side of one of the sync lines.
Sync signal buffer input. Connects to the VGA Controller side of one of the sync lines.
Sync signal buffer output. Connects to the video connector side of one of the sync lines.
ESD protection channel input.
ESD protection channel input.
9
10
11
12
13
14
15
16
DDC_OUT1
DDC_OUT2
SYNC_IN1
SYNC_OUT1
SYNC_IN2
SYNC_OUT2
SD1
SD2
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER
V
CC1
,V
CC2
and V
CC3
Supply Voltage Inputs
Diode Forward Current (one diode conducting at a time)
DC Voltage at Inputs
VIDEO_1, VIDEO_2, VIDEO_3
DDC_OUT1, DDC_OUT2
SYNC_IN1, SYNC_IN2
Operating Temperature Range
Storage Temperature Range
Package Power Rating
RATING
[GND - 0.5] to +6.0
20
[GND - 0.5] to [V
CC1
+ 0.5]
[GND - 0.5] to [V
CC2
+ 0.5]
[GND - 0.5] to [V
CC3
+ 0.5]
0 to +70
-65 to +150
750
UNITS
V
mA
V
V
V
°C
°C
mW
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 04/24/08
●
Fax: 408.263.7846
●
www.cmd.com
3
PACVGA201
Specifications (cont’d)
ELECTRICAL OPERATING CHARACTERISTICS
(SEE NOTE 1)
SYMBOL
I
CC1
I
CC3
PARAMETER
V
CC1
Supply Current
V
CC3
Supply Current
CONDITIONS
V
CC1
= 5.0V
V
CC3
= 5V; SYNC inputs at GND or V
CC3
;
PWR_UP pin at V
CC3
; SYNC ouputs
unloaded
V
CC3
= 5V; SYNC inputs at 3.0V; PWR_UP
pin at V
CC3
; SYNC ouputs unloaded
V
CC3
= 5V; PWR_UP input at GND; SYNC
ouputs unloaded
V
CC2
V
IH
V
IL
V
OH
V
OL
R
B,
R
P
I
IN
V
CC2
Pin Open Circuit
Voltage
Logic High Input Voltage
Logic Low Input Voltage
Logic High Output Voltage
Logic Low Output Voltage
Resistor Value
Input Current
VIDEO_x pins
HSYNC, VSYNC pins
Input Capacitance on
VIDEO_1, VIDEO_2 and
VIDEO_3 pins
SYNC Buffer L => H
Propagation Delay
SYNC Buffer H => L
Propagation Delay
SYNC Buffer Output Rise &
Fall Times
ESD Withstand Voltage
V
CC2
voltage internally derived from V
CC3
via
diode D1; no external current drawn
V
CC3
= 5V; Note 2
V
CC3
= 5V; Note 2
I
OH
= -4mA, V
CC3
= 5.0V; Note 3
I
OL
= 4mA, V
CC3
= 5.0V; Note 3
PWR_UP = V
CC3
= 5.0V
Note 5 applies for all cases.
V
CC1
= 5.0V; V
IN
= V
CC1
or GND
V
CC3
= 5.0V; V
IN
= V
CC3
or GND
Note 5
V
CC1
= 5.0V; V
IN
= 2.5V; measured at 1MHz
V
CC1
= 2.5V; V
IN
= 1.25V; measured at 1MHz
C
L
= 50pF; V
CC3
= 5.0V; Input t
R
and t
F
≤
5ns; Note 5
C
L
= 50pF; V
CC3
= 5.0V; Input t
R
and t
F
≤
5ns; Note 5
C
L
= 50pF; V
CC3
= 5.0V; Input t
R
and t
F
≤
5ns
V
CC1
= V
CC2
= V
CC3
= 5V; Notes 4 & 5
±8
4
4.5
8
8
7.0
12
12
0.5
1
4.4
0.4
2
±1
±1
2.0
0.8
[V
CC3
-0.80]
10
MIN
TYP
MAX
10
UNITS
μA
μA
200
10
μA
μA
V
V
V
V
V
MΩ
μA
μA
pF
pF
ns
ns
ns
kV
C
IN
t
PLH
t
PHL
t
R,
t
F
V
ESD
All parameters specified over standard operating conditions unless otherwise noted.
These parameters apply only to SYNC_IN1, SYNC_IN2 and PWR_UP.
These parameters apply only to SYNC_OUT1 and SYNC_OUT2.
Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. V
CC1
, V
CC2
and V
CC3
must be
bypassed to GND via a low impedance ground plane with a 0.2uF or greater, low inductance, chip ceramic capacitor at each
supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect
to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SD1, SYNC_OUT2, SD2, DDC_OUT1 and
DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body model (MIL-STD-883,
Method 3015).
Note 5: This parameter is guaranteed by design and characterization.
Note 1:
Note 2:
Note 3:
Note 4:
© 2008 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 04/24/08
●
Fax: 408.263.7846
●
www.cmd.com
PACVGA201
Application Information
To Video
DAC V
CC
0.2uF
5V
0.2uF
0.2uF
2
8
1
V
CC1
V
CC2
V
CC3
GND
PWR_UP
6
7
GND
Video Controller
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Green
Blue
VF**
VF**
VF**
11
13
10
9
SYNC_IN1
SYNC_IN2
DDC_OUT2
DDC_OUT1
PACVGA201
SYNC_OUT1
SYNC_OUT2
14
SF**
SF**
12
VF** - VIDEO EMI Filter
SF** - SYNC EMI Filter
3
4
5
VIDEO_1
VIDEO_2
VIDEO_3
SD1
SD2
16
15
Video Connector
H-Sync
V-Sync
DDC_Data
DDC_Clk
Red
Green
Blue
●
Figure 1. Typical Connection Diagram
A resistor may be necessary between the V
CC2
pin and ground if protection against a stream of ESD pulses is
required while the PACVGA201 is in the power-down state. The value of this resistor should be chosen such that
the extra charge deposited into the V
CC2
bypass capacitor by each ESD pulse will be discharged before the next
ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per
second. When the PACVGA201 is in the power-up state, an internal discharge resistor is connected to ground via
a FET switch for this purpose.
For the same reason, V
CC1
and V
CC3
may also require bypass capacitor discharging resistors to ground if there
are no other components in the system to provide a discharge path to ground.
© 2008 California Micro Devices Corp. All rights reserved.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
●
Tel: 408.263.3214
Issue B – 04/24/08
●
Fax: 408.263.7846
www.cmd.com
5
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