HRF-AT4521
31.0 dB, DC - 2.5GHz, 5 Bit Serial Digital Attenuator
The Honeywell HRF-AT4521 is a 5-bit digital attenuator that is ideal for use in
broadband communication system applications that require accuracy, speed and low
power consumption. The HRF-AT4521 is manufactured with Honeywell's patented
Silicon On Insulator (SOI) CMOS manufacturing technology, which provides the
performance of GaAs with the economy and integration capabilities of conventional
CMOS. These attenuators are DC coupled to improve lower operating frequency,
frequency response and reduce the number of DC bias points required.
FEATURES
Very Low DC Power Consumption
Attenuation In Steps From 1 dB To 31 dB
Single Positive Power Supply Voltage
Serial Data Interface
50 Ohm Impedance
DC-coupled, bi-directional RF path
Space Saving VQFN Surface Mount Packaging
Lead-free, RoHS compliant and halogen-free
o
HRF-AT4521 in VQFN Package
RF ELECTRICAL SPECIFICATIONS @ + 25 C (1)
Results @ V
DD
= 5.0 +/- 10%, V
SS
= 0 unless otherwise stated, Z
0
= 50 Ohms
Contact Honeywell for relative performance at other supply configurations
Parameter
Insertion Loss
1dB Compression
Input IP3
V
SS
= 0V, Input Power
V
SS
= - 3V, Input Power
V
SS
= 0V
Two-tone inputs, up to +5 dBm
@ 0 dBm attenuation
V
ss
= -3V
Two-tone inputs, up to + 5 dBm
@ 0 dBm attenuation
Any Combination of Bits
All attenuation states
All attenuation states
All attenuation states
10% To 90%
50% Cntl To 90%/10%RF
T high / T low = ½ minimum clock period
Set up to rising edge of clock
Data hold after rising edge of clock
Data set up to rising edge of OE
50
5
2
5
1.0 GHz
2.0 GHz
2.5 GHz
Test Condition
Frequency
1.0 GHz
2.0 GHz
2.5 GHz
2.0 GHz
2.0 GHz
2.0 GHz
Minimum
Typical
2.0
2.2
2.8
22
28
36
Maximum
2.6
2.8
3.4
Units
dB
dB
dB
dBm
dBm
dBm
Input IP3
Return Loss
Attenuation Accuracy
2.0 GHz
-11
>36
-13
+ (0.25 + 2.5 %), - (0.10 + 5.0 %)
+ 0.45, - (0.20 + 8.0 %)
+ 0.35, - (-0.40 + 10.5%)
10
15
dBm
dB
dB
dB
dB
nS
nS
nS
nS
nS
nS
Trise, Tfall
Ton, Toff (Tpd)
T clock Period (Tprd)
T data set up (Tsup)
T data hold (Thld)
T latch set up (Tlsup)
Note 1 - For higher accuracy designs, please consider HRF-AT4610/HRF-AT4611.
HRF-AT4521
FUNCTIONAL SCHEMATIC
S4
S3
S2
S1
S0
ESD, Buffer, Level Shift
RF In
RF Out
16dB
8dB
4dB
2dB
1dB
DC ELECTRICAL SPECIFICATIONS @ + 25°C
Parameter
Minimum
1
Typical
Maximum
5.5
50
0.8
V
DD
10
Units
V
V
uA
V
V
uA
V
DD
3.3
5.0
V
SS
-5.0
I
DD
<5.0
CMOS Logic level (0)
0
CMOS Logic level (1)
V
DD
– 0.8
Input Leakage Current
Note 1, the performance curves are for V
DD
= +5.0 +/- 10%
ABSOLUTE MAXIMUM RATINGS
1
Parameter
Absolute Maximum
Units
Input Power
+ 35
dBm
V
DD
+6.0
V
V
SS
-5.5
V
2
ESD Voltage
400
V
O
Operating Temperature
-40 To +85
C
O
Storage Temperature
-65 To +125
C
O
Moisture Sensitivity Level
Level 3 @ 260 C
Digital Inputs
V
DD
+0.6 max to -0.6 min
V
Note 1 - Operation of this device beyond any of these parameters may cause permanent damage.
Note 2 - Although the HRF-AT4521 contains ESD protection circuitry on all digital inputs, precautions should be taken to
ensure that the Absolute Maximum Ratings are not exceeded.
Latch-Up:
Unlike conventional CMOS digital attenuators, Honeywell's HRF-AT4521 is immune to latch-up.
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www.honeywell.com/microwave
HRF- AT4521
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
Function
VDD
GROUND
RF INPUT
GROUND
GROUND
GROUND
GROUND
GROUND
Pin
9
10
11
12
13
14
15
16
Function
GROUND
RF OUTPUT
GROUND
VSS
GROUND
OE
CLK
DATA
Note:
Bottom ground plate must be grounded for proper RF performance.
SERIAL DATA LOAD
Serial data is shifted into the register on the rising edge of clock, MSB first. The state of “OE” will not affect the shifting of
data. The rising edge of the “OE” signal will be the clock for the transfer of shifted data. Latched new data occurs one
prop delay after the rising edge of “OE”. See the Electrical Spec Table for AC parameters.
TRUTH TABLE
S4
0
0
0
0
0
1
1
S3
0
0
0
0
1
0
1
S2
0
0
0
1
0
0
1
S1
0
0
1
0
0
0
1
S0
0
1
0
0
0
0
1
Output
Reference Input
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
Operation: Data on serial input D is clocked into internal registers on the low to high transition of the Clock signal (CK).
The register output is enabled when Output Enable (OE) is in the low state.
"0" = CMOS Low, "1" = CMOS High.
www.honeywell.com/microwave
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