DATA BULLETIN
MX609
Features
Single Chip full Duplex CVSD CODEC
On-chip Input and Output Filters
Programmable Sampling Clocks
3- or 4-bit Companding Algorithm
Powersave Capabilities
Low Power, 5.0V Operation
PCN/PCS DELTA
MODULATION CODEC
Applications
Digital PCN/PCS Systems
Digital Cordless Phones
Digital Delay Lines
Digital Voice Storage
Multiplexers, Switches, and
Phones
Time Domain Scramblers
DATA ENABLE
ENCODER FORCE IDLE*
ENCODER INPUT
V
DD
V
SS
XTAL/CLOCK
XTAL
ENCODER DATA CLOCK
DECODER DATA CLOCK
V
BIAS
MODE 1
MODE 2
ALGORITHM
POWERSAVE
DECODER INPUT
CLOCK MODE
LOGIC
ENCODER
OUTPUT
MOD
f
1
f
0
CLOCK RATE
GENERATORS
f
2
SAMPLING RATE
CONTROL
3 or 4 BIT
f
3
DEMOD
f
1
DECODER
OUTPUT
DECODER FORCE IDLE*
*Available on J,P & LH
package styles only
The MX609 is a Continuously Variable Slope Delta Modulation (CVSD) Codec designed for use in cordless
telephones. The device is suitable for applications in delta multiplexers, switches and phones. Encoder input
and decoder output switched capacitor filters are incorporated on-chip.
Sampling clock rates can be programmed to 16, 32 or 64K bits/second from an internal clock generator or
externally injected in the 8 to 64K bits/second range. The internal clocks are derived from an on-chip
reference oscillator driven by an externally connected crystal. The sampling clock frequency is output for the
synchronization of external circuits.
The encoder has an enable function for use in multiplexer applications. When not enabled the encoder output
remains in a high-impedance “tri-state” mode.
Companding circuits may be operated with an externally selectable 3- or 4-bit algorithm. The device may be
put in standby mode when Powersave is selected.
The MX609 operates with a supply voltage of 5.0V and is available in the following packages: 24-pin PLCC
(MX609LH), 16-pin SOIC (MX609DW), 22-pin CERDIP (MX609J), and 22-pin PDIP (MX609P).
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All Trademarks and service marks are held by their respective companies.
PCN/PCS Delta Modulation CODEC
2
MX609
CONTENTS
Section
Page
1 Block Diagram................................................................................................................ 3
2 Signal List....................................................................................................................... 4
3 External Components.................................................................................................... 6
4 General Description....................................................................................................... 6
5 Application ..................................................................................................................... 7
5.1
5.2
CODEC Integration.............................................................................................................. 7
CODEC Performance .......................................................................................................... 7
6 Performance Specification............................................................................................ 9
6.1
Electrical Performance ........................................................................................................ 9
6.1.1
6.1.2
6.1.3
6.1.4
Absolute Maximum Ratings.................................................................................................... 9
Operating Limits ..................................................................................................................... 9
Operating Characteristics..................................................................................................... 10
TIMING................................................................................................................................. 11
6.2
Packaging.......................................................................................................................... 12
MX-COM, Inc. reserves the right to change specifications at any time and without notice.
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All Trademarks and service marks are held by their respective companies.
PCN/PCS Delta Modulation CODEC
3
MX609
1 Block Diagram
DATA ENABLE
ENCODER FORCE IDLE*
ENCODER INPUT
V
DD
V
SS
XTAL/CLOCK
XTAL
ENCODER DATA CLOCK
DECODER DATA CLOCK
V
BIAS
MODE 1
MODE 2
ALGORITHM
POWERSAVE
DECODER INPUT
CLOCK MODE
LOGIC
ENCODER
OUTPUT
MOD
f
1
f
0
CLOCK RATE
GENERATORS
f
2
SAMPLING RATE
CONTROL
3 or 4 BIT
f
3
DEMOD
f
1
DECODER
OUTPUT
DECODER FORCE IDLE*
*Available on J,P & LH
package styles only
Figure 1: Block Diagram
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All Trademarks and service marks are held by their respective companies.
PCN/PCS Delta Modulation CODEC
4
MX609
2 Signal List
1
1
1
Xtal/Clock
input
Input to the clock oscillator inverter. A 1.024MHz Xtal input
or externally derived clock is injected here. See Clock Mode
pins and figure 3.
The 1.024 MHz output of the clock oscillator inverter.
No Connection
A logic I/O port. External encode clock input or internal data
clock output. Clock frequency is dependent upon Clock
Mode 1, 2 inputs and Xtal frequency (see Clock Mode pins).
The encoder digital output. This is a three-state output
whose condition is set by the Data Enable and
Powersave inputs. See Table 2:
When this pin is at a logical “0” the encoder is forced to an
idle state and the encoder digital output is 0101, a perfect
idle pattern. When this pin is a logical “1” the encoder
encodes as normal. Internal 1M pullup.
Data is made available at the encoder output pin by control
of this input. See Encoder Output pin. Internal 1 M pullup.
No Connection
Normally at V
DD
/2 bias, this pin should be externally
decoupled by capacitor C4. Internally pulled to V
SS
when
“ Powersave ” is a logical “0”.
The analog signal input. Internally biased at V
DD
/2, this
input requires an external coupling capacitor. The source
impedance should be less than 100. Output channel noise
levels will improve with an even lower source impedance.
See Figure 3.
Negative Supply
No Connection
The recovered analog signal is output at this pin. It is the
buffered output of a lowpass filter and requires external
components. During “Powersave” this output is open circuit.
No Connection
A logic “0” at this pin puts most parts of the codec into a
quiescent non-operational state. When at a logical “1”, the
codec operates normally. Internal 1 M pullup.
No Connection
A logic “0” at this pin gates a 0101... pattern internally to the
decoder so that the Decoder Output goes to V
DD
/2. When
this pin is a logical “1” the decoder operates as normal.
Internal 1M pullup.
The received digital signal input. Internal 1 M pullup.
A logic I/O port. External decode clock input or internal data
clock output, dependent upon clock mode 1,2 inputs. See
Clock Mode pins.
A logic “1” at this pin sets this device for a 3-bit companding
algorithm. A logical “0” sets a 4-bit companding algorithm.
Internal 1 M pullup.
2
3
4
2
3
4
5
N/C
2
3
Xtal
N/C
Encoder Data
Clock
Encoder Output
output
input/
output
output
5
6
4
6
7
-
Encoder Force Idle
7
8
9
8
9
10
5
Data Enable
N/C
Bias
input
6
10
11
7
Encoder Input
input
11
12
13
12
13
14
8
-
9
V
SS
N/C
Decoder Output
power
output
14
15
15
16
N/C
10
Powersave
16
17
18
-
Decoder Force Idle
17
18
19
20
11
12
Decoder Input
Decoder Data
Clock
Algorithm
input/
output
19
21
13
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All Trademarks and service marks are held by their respective companies.
PCN/PCS Delta Modulation CODEC
5
MX609
20
21
22
23
14
15
Clock Mode 2
Clock Mode 1
22
24
16
V
DD
power
Clock rates refer to f = 1024MHz Xtal/Clock input. During
internal operation the data clock frequencies are available at
the ports for external circuit synchronization. Independent
or common data rate inputs to Encode and Decode data
clock ports may be employed in the External Clocks mode.
Internal 1M pullups.
Positive Supply. A single 5.0V supply is required.
Table 1: Signal List
Data Enable
1
0
1
Powersave
1
1
0
Encoder Output
Enable
High Z (open circuit)
V
SS
Table 2: Encoder Output
Clock Mode 1
0
0
1
1
Clock Mode 2
0
1
0
1
Facility
External Clocks
Internal, 64kbps = f/16
Internal, 32kbps = f/32
Internal, 16kbps = f/64
Table 3: Clock Mode
1998
MX-COM, Inc.
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 204800069.005
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All Trademarks and service marks are held by their respective companies.
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