CAT24C208
8 kb Dual Port Serial
EEPROM
Description
The CAT24C208 is an 8 kb Dual Port Serial CMOS EEPROM
internally organized as 4 segments of 256 bytes each. The
CAT24C208 features a 16−byte page write buffer and can be accessed
from either of two separate I
2
C compatible ports, DSP (SDA, SCL)
and DDC (SDA, SCL).
Arbitration between the two interface ports is automatic and allows
the appearance of individual access to the memory from each
interface.
Features
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SOIC−8
W SUFFIX
CASE 751BD
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•
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Supports Standard and Fast I
2
C Protocol
2.5 V to 5.5 V Operation
16−Byte Page Write Buffer
Schmitt Triggers and Noise Protection Filters on I
2
C Bus Input
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
SOIC 8−lead Package
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
PIN CONFIGURATION
DSP V
CC
DSP SCL
DSP SDA
V
SS
SOIC (W)
(Top View)
1
DDC V
CC
EDID SEL
DDC SCL
DDC SDA
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
DSP V
CC
ARBITRATION
LOGIC
DDC V
CC
DSP SCL
DSP SDA
DISPLAY
CONTROL
LOGIC
D
E
C
O
D
E
R
S
1K X 8
MEMORY
ARRAY
D
E
C
O
D
E
R
S
DDC
CONTROL
LOGIC
DDC SCL
DDC SDA
V
SS
CONFIGURATION
REGISTER
EDID SEL
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2009
September, 2009
−
Rev. 6
1
Publication Order Number:
CAT24C208/D
CAT24C208
Table 1. PIN DESCRIPTION
Pin Number
1
2
3
Pin Name
DSP V
CC
DSP SCL
DSP SDA
Device power from display controller
The CAT24C208 DSP serial clock bidirectional pin is used to clock all data transfers into or out of the
device DSP SDA pin and is also used to block DSP Port access when DDC Port is active.
DSP Serial Data/Address. The bidirectional DSP serial data/address pin is used to transfer data into
and out of the device from a display controller. The DSP SDA pin is an open drain output and can be
wireOR’ed with other open drain or open collector outputs.
Device ground.
DDC Serial Data/Address. The bidirectional DDC serial data/address pin is used to transfer data into
and out of the device from a DDC host. The DDC SDA pin is an open drain output and can be wire−
OR’ed with other open drain or open collector outputs.
The CAT24C208 DDC serial clock bidirectional pin is used to clock all data transfers into or out of the
device DDC SDA pin, and is used to block DDC Port for access when DSP Port is active.
EDID select. The CAT24C208 EDID select input selects the active bank of memory to be accessed
via the DDC SDA/SCL interface as set in the configuration register.
Device power when powered from a DDC host.
Function
4
5
V
SS
DDC SDA
6
7
8
DDC SCL
EDID SEL
DDC V
CC
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
Ratings
–55 to +125
–65 to +150
–2.0 to +V
CC
+2.0
–2.0 to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 3. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Note 3)
T
DR
(Note 3)
V
ZAP
(Note 3)
I
LTH
(Notes 3 and 4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−up
Reference Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
JEDEC Standard JESD 22
JEDEC Standard 17
Min
1,000,000
100
2000
100
Units
Cycles/Byte
Years
Volts
mA
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
Table 4. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 5)
C
IN
(Note 5)
Parameter
Input/Output Capacitance (Either DSP or DDC SDA)
Input Capacitance (EDID, Either DSP or DDC SCL)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
6
Units
pF
pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT24C208
Table 5. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
I
CC
I
SB
I
LI
I
LO
V
IL
V
IH
VHYS
V
OL1
V
CCL1
V
CCL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Hysteresis
Output Low Voltage (V
CC
= 3 V)
Leakage DSP V
CC
to DDC V
CC
Leakage DDC V
CC
to DSP V
CC
I
OL
= 3 mA
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or either DSP or DDC V
CC
V
IN
= GND to either DSP or DDC V
CC
V
OUT
= GND to either DSP or DDC V
CC
−1
V
CC
x 0.7
0.05
0.4
±100
±100
Min
Typ
Max
3
50
10
10
V
CC
x 0.3
V
CC
+ 0.5
Units
mA
mA
mA
mA
V
V
V
V
mA
mA
Table 6. A.C. CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, unless otherwise specified.)
Symbol
READ & WRITE CYCLE LIMITS
F
SCL
T
I
(Note 6)
t
AA
t
BUF
(Note 6)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 6)
t
F
(Note 6)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out and ACK Out
Time the Bus Must be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.6
100
1.3
0.6
1.3
0.6
0.6
0
100
300
300
400
100
0.9
kHz
ns
ms
ms
ms
ms
ms
ms
ns
ns
ns
ns
ms
ns
Parameter
Min
Max
Units
Table 7. POWER−UP TIMING
(Notes 6 and 7)
Symbol
t
PUR
t
PUW
Parameter
Power−up to Read Operation
Power−up to Write Operation
Min
Typ
Max
1
1
Units
ms
ms
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 8. WRITE CYCLE LIMITS
Symbol
t
WR
Parameter
Write Cycle Time
Min
Typ
Max
5
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond
to its slave address.
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CAT24C208
Functional Description
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I
2
C interface ports,
(DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL), and with the use of segment pointer at address
60h. On power up and after any instruction, the segment
pointer will be in segment 00h for DSP and in segment 00h
of the bank selected by the configuration register for DDC.
The entire memory appears as contiguous memory space
from the perspective of the display interface (DSP_SDA and
DSP_SCL), see Figure 4, and Figures 14 to Figure 21 for a
complete description of the DSP Interface.
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device as
seen from the DDC interface, (DDC_SDA and DDC_SCL).
Read and write operations can be performed on any
location within the memory space from the display DSP
interface regardless of the state of the EDID SEL pin or the
activity on the DDC interface. From the DDC interface, the
memory space appears as two 512 byte banks of memory,
with 2 segments each 00h and 01h in the upper and lower
bank, see Figure 3.
Each bank of memory can be used to store an E−EDID
data structure. However, only one bank can be read through
the DDC port at a time. The active bank of memory (that is,
the bank that appears at address A0h on the DDC port) is
controlled through the configuration register at 62/63h and
the EDID_SEL pin.
No write operations are possible from the DDC interface
unless the DDC Write Enable bit is set (WE = 1) in the device
configuration register at device address 62h.
The device automatically arbitrates between the two
interfaces to allow the appearance of individual access to the
memory from each interface.
In a typical E−EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual−mode (analog and digital)
display. In this manner, the E−EDID appearing at address
A0h on the DDC port will be either the analog or digital
E−EDID, depending on the state of the “Analog Cable
Detect” pin (pin C3 of the M1−DA connector). See Figure 2.
+5V DC
(SUPPLIED
BY DISPLAY)
10K
8
7
E−EDID
6 EEPROM
5
1
2
3
4
28
DDC +5V
M1−DA CONNECTOR
47.5K
C3
27
26
DDC CLK
DDC DATA
TO HOST
CONTROLLER
I
2
C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
Fuse, Resistor or Other Current
Limiting Device Required in All
M1 Displays
8
HPD
2A MAX
RELAY CONTACTS SHOWN IN
DE−ENERGIZED POSITION
Figure 2.
MEMORY ARRAY
01
Upper
Bank
00
01
Lower
Bank
00
Segment 1
256 Bytes
Segment 0
256 Bytes
Segment 1
256 Bytes
Segment 0
256 Bytes
No Segment Pointer
00
00
11
10
01
00
MEMORY ARRAY
Segment 3
256 Bytes
Segment 2
256 Bytes
Segment 1
256 Bytes
Segment 0
256 Bytes
00
Segment Pointer
Address by Configuration
Register (see Table 10)
Segment Pointer
No Segment Pointer
Figure 3. DDC Interface
Figure 4. DSP Interface
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CAT24C208
I
2
C Bus Protocol
The following defines the features of the I
2
C bus protocol:
1. Data transfer may be initiated only when the bus is
not busy.
2. During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is high
will be interpreted as a START or STOP condition.
Acknowledge
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of either
SDA when the respective SCL is HIGH. The CAT24C208
monitors the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
After a successful data transfer, each receiving device is
required to generate an acknowledge. The acknowledging
device pulls down the respective SDA line during the ninth
clock cycle, signaling that it received the 8 bits of data.
The CAT24C208 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8−bit
byte.
When the CAT24C208 is in a READ mode it transmits 8
bits of data, releases the respective SDA line, and monitors
the line for an acknowledge. Once it receives this
acknowledge, the CAT24C208 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
After an unsuccessful data transfer an acknowledge will
not be issued (NACK) by the slave (CAT24C208), and the
master should abort the sequence. If continued the device
will read from or write to the wrong address in the two
instruction format with the segment pointers.
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
1
8
9
BUS RELEASE DELAY
(RECEIVER)
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP
ACK DELAY
Figure 5. Acknowledge Timing
Device Addressing
DDC Interface
Both the DDC and DSP interfaces to the device are based
on the I
2
C bus serial interface. All memory space operations
are done at the A0/A1 DDC address pair. As such, all write
operations to the memory space are done at DDC address
A0h and all read operations of the memory space are done
at DDC address A1h.
Figure 6 shows the bit sequence of a random read from
anywhere within the memory space. The word offset
determines which of the 256 bytes within segment 00h is
being read. Here the segment 00h can be at the lower or
upper bank depending on the configuration register.
Sequential reads can be done in much the same manner by
reading successive bytes after each acknowledge without
generating a stop condition. See Figure 7. The device
automatically increments the word offset value (8−bit value)
and with wraparound in the same segment 00h to read
maximum of 256 bytes.
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