PCA85232
LCD driver for low multiplex rates
Rev. 4 — 8 April 2015
Product data sheet
1. General description
The PCA85232 is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)
1
with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 160 segments. It can easily
be cascaded for larger LCD applications. The PCA85232 is compatible with most
microcontrollers and communicates via the two-line bidirectional I
2
C-bus. Communication
overheads are minimized by a display RAM with auto-incremental addressing, by
hardware subaddressing, and by display memory switching (static and duplex drive
modes).
For a selection of NXP LCD segment drivers, see
Table 29 on page 56.
2. Features and benefits
AEC-Q100 compliant for automotive applications
Single-chip LCD controller and driver for up to 640 elements
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
160 segment drives:
Up to 80 7-segment numeric characters
Up to 40 14-segment alphanumeric characters
Any graphics of up to 640 elements
May be cascaded for large LCD applications (up to 5120 elements possible)
160
4-bit RAM for display data storage
Software programmable frame frequency in the range of 117 Hz to 176 Hz; factory
calibrated
Wide LCD supply range: from 1.8 V for low threshold LCDs and up to 8.0 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
Internal LCD bias generation with voltage-follower buffers
Selectable display bias configuration: static,
1
⁄
2
, or
1
⁄
3
Wide power supply range: from 1.8 V to 5.5 V
LCD and logic supplies may be separated
Low power consumption, typical: I
DD
= 4
A,
I
DD(LCD)
= 65
A
400 kHz I
2
C-bus interface
Auto-incremental display data loading across device subaddress boundaries
Versatile blinking modes
Compatible with Chip-On-Glass (COG) technology
No external components required
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in
Section 19 on page 58.
NXP Semiconductors
PCA85232
LCD driver for low multiplex rates
Two sets of backplane outputs for optimal COG configurations of the application
3. Ordering information
Table 1.
Ordering information
Package
Name
PCA85232U
bare die
Description
197 bumps; 6.5
1.16
0.40 mm
Version
PCA85232U
Type number
3.1 Ordering options
Table 2.
Ordering options
Orderable part number Sales item
(12NC)
PCA85232U/2DA/Q1,0
935291553026
Delivery form
chips with bumps in tray
IC
revision
1
Product type number
PCA85232U/2DA/Q1
4. Marking
Table 3.
Marking codes
Marking code
PC85132/232-1
Product type number
PCA85232U
PCA85232
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2015
2 of 65
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Product data sheet
Rev. 4 — 8 April 2015
4 of 65
PCA85232
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
NXP Semiconductors
6. Pinning information
6.1 Pinning
LCD driver for low multiplex rates
PCA85232
Viewed from active side. For mechanical details, see
Figure 37 on page 49.
Fig 2.
Pinning diagram of PCA85232
NXP Semiconductors
PCA85232
LCD driver for low multiplex rates
6.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (V
SS
or V
DD
) unless otherwise specified.
Symbol
SDAACK
[1]
SDA
[1]
SCL
CLK
V
DD
SYNC
OSC
T1, T2, and T3
A0 and A1
SA0
V
SS[2]
V
LCD
BP2 and BP0
S0 to S79
BP0, BP2, BP1, and BP3
S80 to S159
BP3 and BP1
[1]
[2]
Pin
1 to 3
4 to 6
7 to 9
10
11 to 13
14
15
16, 17, and 18 to 20
21, 22
23
24 to 26
27 to 29
30, 31
32 to 111
112 to 115
116 to 195
196, 197
Description
I
2
C-bus acknowledge output
I
2
C-bus serial data input
I
2
C-bus serial clock input
clock input and output
supply voltage
cascade synchronization input and output
selection of internal or external clock
dedicated testing pins; to be tied to V
SS
in
application mode
subaddress inputs
I
2
C-bus slave address input
ground supply voltage
LCD supply voltage
LCD backplane outputs
LCD segment outputs
LCD backplane outputs
LCD segment outputs
LCD backplane outputs
For most applications SDA and SDAACK are shorted together (see
Section 14.3 on page 44).
The substrate (rear side of the die) is connected to V
SS
and should be electrically isolated.
PCA85232
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 8 April 2015
5 of 65
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