White Electronic Designs
4Mx32 5V FLASH MODULE
FEATURES
Access Times of 100, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
• 68 lead, 40mm Low Profile CQFP (Package
502), 3.5mm (0.140") height.
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height.
Designed to
fi
t JEDEC 68 lead 0.990CQFJ
footprint (Fig. 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8
chip
• Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 4Mx32
WF4M32-XXX5
PRELIMINARY*
User configurable as 2x4Mx16 or 4x4Mx8 in HIP
and G4T packages.
Commercial, Industrial, and Military Temperature
Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Separate Power and
Ground Planes to improve noise immunity
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
FIGURE 1 – PIN CONFIGURATION FOR WF4M32-XH2X5
PIN DESCRIPTION
Top View
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
22
12
RESET#
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
17
WE#
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
7
A
12
A
21
A
13
A
8
I/O
16
I/O
17
I/O
18
34
V
CC
CS
4#
NC
I/O
27
A
4
A
5
A
6
A20
CS
3#
GND
I/O
19
44
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
I/O
23
I/O
22
I/O
21
I/O
20
55
56
CS
2#
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1#
A
19
I/O
3
I/O
0-31
A
0-21
WE#
CS
1-4
#
OE#
V
CC
V
SS
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
Block Diagram
CS1#
A
21
CS2#
CS3#
CS4#
OE#
WE#
A
0-20
RESET#
2M x 8
2M x 8
2Mx 8
2M x 8
2M
x 8
2M
x 8
2M
x 8
2M
x 8
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
June 2004
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WF4M32-XXX5
PRELIMINARY
FIGURE 2 – PIN CONFIGURATION FOR WF4M32-XG4TX5
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
#
GND
CS
3
#
WE#
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-21
WE#
CS
1-4
#
OE#
V
CC
GND
RESET#
NC
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
BLOCK DIAGRAM
CS1#
A
21
CS2#
CS3#
CS4#
OE#
WE#
A
0-20
RESET#
2M x 8
2M x 8
2M x 8
2M x 8
BUFFER
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
#
OE#
CS
4
#
A
17
A
18
A
19
A
20
RESET#
NC
A21
2M
x 8
2M
x 8
2M
x 8
2M
x 8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
FIGURE 3 – PIN CONFIGURATION FOR WF4M32-XG2TX5
TOP VIEW
RESET#
A
0
A
1
A
2
A
3
A
4
A
5
NC
GND
NC
WE#
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-21
WE#
CS
1-2
#
OE#
V
CC
GND
RESET#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
Reset
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
The White 68 lead G2T CQFP
fi
lls the
same
fi
t and function as the JEDEC 68 lead
CQFJ or 68 PLCC. But the G2T has the
TCE and lead inspection advantage of the
CQFP form.
Block Diagram
CS
1 #
RESET#
WE#
OE#
A
0-20
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
CS
1
#
OE#
CS
2
#
V
CC
A
11
A
17
NC
NC
NC
A
12
A
13
A
14
A
15
A
16
A
18
A
19
A
20
CS
2 #
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
Note: CS1#& CS2# are used as bank select
June 2004
Rev. 6
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Short Circuit Output Current
Endurance — write/erase cycles
Data Retention (Mil Temp)
WF4M32-XXX5
PRELIMINARY
CAPACITANCE
T
A
= +25°C, V
IN
= OV,
F
= 1.0MHz
Unit
V
W
°C
mA
cycles
years
Symbol
V
T
P
T
T
STG
I
OS
(Mil Temp)
Ratings
-2.0 to +7.0
8
-65 to +125
100
100,000 min.
20
Parameter
OE# capacitance
WE# capacitance
CS# capacitance
Data I/O capacitance
Address input capacitance
Symbol HIP (H2) CQFP (G2T) CQFP(G4T)
75
75
20
C
OE
75
75
20
C
WE
20
50
20
C
CS
30
30
30
C
I/O
75
75
20
C
AD
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
Symbol
V
CC
V
SS
V
IH
V
IL
T
A
T
A
Min
4.5
0
2.0
-0.5
-55
-40
Typ
5.0
0
–
–
–
–
Max
5.5
0
V
CC
+ 0.5
+0.8
+125
+85
Unit
V
V
V
V
°C
°C
DC CHARACTERISTICS - CMOS COMPATIBLE
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
HIP
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program
or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Symbol
I
LI
I
LOX32
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz
CS# = V
IL
, OE# = V
IH
V
CC
= 5.5, CS# = V
IH
,
f = 5MHz, RESET# = V
IH
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
Min
Max
10
10
320
420
20
0.45
0.85 x
V
CC
3.2
0.85 x
V
CC
3.2
Min
G2T
Max
10
10
215
295
2.0
0.45
0.85 x
V
CC
3.2
Min
G4T
Max
10
10
345
445
95
0.45
Unit
μA
μA
mA
mA
mA
V
V
V
4.2
4.2
4.2
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency
dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
HIP = 66 pin, PGA Type, 1.385" square, Hermetic Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square. Designed to
fi
t JEDEC 68
lead 0.990" CQFJ footprint (Fig. 3) (Package 509)
G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140") (Package 502 )
June 2004
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
V
CC
= 5.0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
V
CC
Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET# Pulse Width
NOTES:
1. Typical value for t
WHWH1
is 7μs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
WF4M32-XXX5
PRELIMINARY
AC Characteristics – Write/Erase/Program Operations - WE# Controlled
Symbol
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
Min
100
0
45
0
45
0
45
20
-100
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
sec
μs
μs
sec
sec
ns
ns
300
15
0
50
44
256
t
OEH
t
RP
10
500
10
500
0
50
300
15
0
50
44
256
10
500
300
15
44
256
AC CHARACTERISTICS – READ-ONLY OPERATIONS
V
CC
= 5.0V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS# or OE# Change,
whichever is First
RESET# Low to Read Mode (1)
1. Guaranteed by design, not tested.
Symbol
Min
T
AVAV
T
AVQV
T
ELQV
T
GLQV
T
EHQZ
T
GHQZ
T
AXQX
T
RC
T
ACC
T
CE
T
OE
T
DF
T
DF
T
OH
T
READY
0
100
-1000
Max
100
100
40
20
20
Min
120
-120
Max
120
120
50
30
30
Min
150
-150
Unit
Max
ns
150
150
55
35
35
ns
ns
ns
ns
ns
ns
20
μs
0
20
20
0
June 2004
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WF4M32-XXX5
PRELIMINARY
AC CHARACTERISTICS FOR G2T PACKAGE – WRITE/ERASE/PROGRAM OPERATIONS,
CS# CONTROLLED
V
CC
= 5.0V, GND = 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
0
44
Symbol
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
Min
100
0
45
0
45
0
45
20
-100
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
300
15
0
300
15
0
44
300
15
44
μs
sec
μs
sec
Chip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for t
WHWH1
is 7μs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
t
OEH
10
256
10
256
10
256
sec
ns
June 2004
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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