Product Brief
MX25L1005, MX25L2005
1M/2M-BIT [x 1] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface (SPI) compatible -- Mode 0
and Mode 3
• 2,097,152 x 1 bit structure for 2M; 1,048,576 x 1 bit
structure for 1M
• 32 Equal Sectors with 4K byte each (MX25L1005)
64 Equal Sectors with 4K byte each (MX25L2005)
- Any Sector can be erased individually
• 4 Equal Blocks with 64K byte each (MX25L1005)
8 Equal Blocks with 64K byte each (MX25L2005)
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz and 66MHz serial clock
(30pF + 1TTL Load)
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page
(256-byte per page)
- Fast erase time: 90ms(typ.) and 270ms(max.)/sector
(4K-byte per sector) ; 1s(typ.) and 3s(max.)/block (64K-
byte per block)
• Low Power Consumption
- Low active read current: 8mA(max.) at 66MHz and
4mA(max.) at 20MHz
- Low active programming current: 30mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 50uA (max.)
- Deep power-down mode 10uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area
to be software protected against Program and Erase
instructions.
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected
sector
-
Automatically programs and verifies data at selected
page by an internal algorithm that automatically times
the program pulse widths (Any page to be programed
should have page in the erased state first)
•
Status Register Feature
•
Electronic Identification
-
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
•
SCLK Input
-
Serial clock input
• SI Input
-
Serial Data Input
• SO Output
-
Serial Data Output
• WP# pin
-
Hardware write protection
• HOLD# pin
-
pause the chip without diselecting the chip
• PACKAGE
-
8-pin SOP (150mil)
- 8-land SON (6x5mm)
01/14/2005
1
MX25L1005, MX25L2005
GENERAL DESCRIPTION
The MX25L1005 is a CMOS 1,048,576 bit serial Flash
memory, which is configured as 131,072 x 8 internally. The
MX25L2005 is a CMOS 2,097,152 bit serial Flash memory,
which is configured as 262,144 x 8 internally. The
MX25L1005 and MX25L2005 feature a serial peripheral
interface and software protocol allowing operation on a
simple 3-wire bus. The three bus signals are a clock input
(SCLK), a serial data input (SI), and a serial data output
(SO). SPI access to the device is enabled by CS# input.
The MX25L1005 and MX25L2005 provide sequential read
operation on whole chip.
After program/erase command is issued, auto program/
erase algorithms which program/ erase and verify the
specified page or byte /sector/block locations will be
executed. Program command is executed on page (256
bytes) basis, and erase command is executes on chip or
sector(4K-bytes) or block(64K-bytes).
To provide user with ease of interface, a status register is
included to indicate the status of the chip. The status read
command can be issued to detect completion and error flag
status of a program or erase operation.
When the device is not in operation and CS# is high, it is
put in standby mode and draws less than 50uA DC current.
The MX25L1005 and MX25L2005 utilize MXIC's propri-
etary memory cell, which reliably stores memory contents
even after 100,000 program and erase cycles.
PIN CONFIGURATIONS
8-PIN SOP (150mil) and 8-LAND SON (6x5mm)
PIN DESCRIPTION
SYMBOL
CS#
SI
SO
SCLK
HOLD#
VCC
GND
DESCRIPTION
Chip Select
Serial Data Input
Serial Data Output
Clock Input
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
Ground
CS#
SO
WP#
GND
1
2
3
4
8
7
6
4
VCC
HOLD#
SCLK
SI
2
1/14/2005
MX25L1005, MX25L2005
BLOCK DIAGRAM
Address
Generator
X-Decoder
Memory Array
Page Buffer
Data
Register
Y-Decoder
SRAM
Buffer
Sense
Amplifier
HV
Generator
SI
CS#
Mode
Logic
State
Machine
Output
Buffer
SO
SCLK
Clock Generator
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MX25L1005, MX25L2005
DATA PROTECTION
The MX25L1005, MX25L2005 are designed to offer
protection against accidental erasure or programming
caused by spurious system level signals that may exist
during power transition. During power up the device
automatically resets the state machine in the Read mode.
In addition, with its control register architecture, alteration
of the memory contents only occurs after successful
completion of specific command sequences. The device
also incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and power-down
transition or system noise.
• Power-On Reset and an internal timer (tPUW) can
provide protection against inadvertant changes while
the power supply is outside the operating specification.
•
Program, Erase and Write Status Register instructions
are checked that they consist of a number of clock
pulses that is a multiple of eight, before they are
accepted for execution.
• To avoid unexpected changes by system power supply
transition, the Power-On Reset and an internal timer
(tPUW) can protect the device.
• Before the Program, Erase, and Write Status Register
execution, instruction length will be checked on follow-
ing the clock pulse number to be multiple of eight base.
• Write Enable (WREN) instruction must set to Write
Enable Latch (WEL) bit before writing other instructions
to modify data. The WEL bit will return to reset state by
following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
• The Software Protected Mode (SPM) use (BP1, BP0)
bits to allow part of memory to be protected as read
only.
• The Hardware Protected Mode (HPM) use WP# to
protect the (BP1, BP0) bits and SRWD bit.
• Deep-Power Down Mode also protects the device by
ignoring all instructions except Release from Deep-
Power Down (RDP) instruction and RES instruction.
• All instructions that modify data must be preceded by
a Write Enable (WREN) instruction to set the Write
Enable Latch (WEL) bit . This bit is returned to its reset
state by the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
•
The Block Protect (BP1, BP0) bits allow part of the
memory to be configured as readonly. This is the
Software Protected Mode (SPM).
The Write Protect (WP#) signal allows the Block
Protect (BP1, BP0) bits and Status Register Write
Disable (SRWD) bit to be protected. This is the Hard-
ware Protected Mode (HPM).
In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protec-
tion from inadvertent Write, Program and Erase in-
structions, as all instructions are ignored except one
particular instruction (the Release from Deep
Powerdown instruction).
•
•
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1/14/2005
MX25L1005, MX25L2005
M
ACRONIX
I
NTERNATIONAL
C
O.,
L
TD.
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TEL:+886-3-578-6688
FAX:+886-3-563-2888
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M
ACRONIX
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MERICA,
I
NC.
TEL:+1-408-262-8887
FAX:+1-408-262-8810
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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