Changes to Figure 40 and Figure 41 ............................................. 15
Changes to Ordering Guide .......................................................... 16
5/03—Revision 0: Initial Version
Rev. B | Page 2 of
16
AD5160
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= +V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.
Table 1.
Parameter
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
Potentiometer Divider Mode
Resolution
Differential Nonlinearity
4
Integral Nonlinearity
4
Voltage Divider Temperature Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
5
Capacitance A, Capacitance B
6
Capacitance W
6
Common-Mode Leakage
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 8
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time
Resistor Noise Voltage Density
1
2
Symbol
Conditions
Min
Typ
1
Max
Unit
R-DNL
R-INL
∆R
AB
∆R
AB
/∆T
R
W
N
DNL
INL
∆V
W
/∆T
V
WFSE
V
WZSE
V
A,
V
B,
V
W
C
A,B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
P
DISS
PSS
BW_5K
THD
W
t
S
e
N_WB
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
, wiper = no connect
Specifications apply to all VRs
−1.5
−4
−20
±0.1
±0.75
45
50
+1.5
+4
+20
120
8
+1.5
+1.5
0
+6
V
DD
LSB
LSB
%
ppm/°C
Ω
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
V
V
V
V
μA
pF
V
μA
mW
%/%
MHz
%
μs
nV/√Hz
−1.5
−1.5
Code = 0x80
Code = 0xFF
Code = 0x00
−6
0
GND
f = 1 MHz, measured to GND, code = 0x80
f = 1 MHz, measured to GND, code = 0x80
V
A
= V
B
= V
DD
/2
2.4
±0.1
±0.6
15
−2.5
+2
45
60
1
0.8
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
2.1
0.6
±1
5
2.7
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
∆V
DD
= +5 V ± 10%, code = midscale
R
AB
= 5 kΩ, code = 0x80
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
V
A
= 5 V, V
B
= 0 V, ±1 LSB error band
R
WB
= 2.5 kΩ
3
±0.02
1.2
0.05
1
6
5.5
8
0.2
±0.05
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). V
A
= V
DD
and V
B
=
0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
Rev. B | Page 3 of 16
AD5160
10 kΩ, 50 kΩ, 100 kΩ VERSIONS
V
DD
= 5 V ± 10%, or 3 V ± 10%; V
A
= V
DD
; V
B
= 0 V; −40°C < T
A
< +125°C; unless otherwise noted.
Table 2.
Parameter
DC CHARACTERISTICS
Rheostat Mode
Resistor Differential Nonlinearity
2
Resistor Integral Nonlinearity
2
Nominal Resistor Tolerance
3
Resistance Temperature Coefficient
Wiper Resistance
Potentiometer Divider Mode
Resolution
Differential Nonlinearity
4
Integral Nonlinearity
4
Voltage Divider Temperature
Coefficient
Full-Scale Error
Zero-Scale Error
RESISTOR TERMINALS
Voltage Range
5
Capacitance A, Capacitance B
6
Capacitance W
6
Common-Mode Leakage
DIGITAL INPUTS
Input Logic High
Input Logic Low
Input Logic High
Input Logic Low
Input Current
Input Capacitance
6
POWER SUPPLIES
Power Supply Range
Supply Current
Power Dissipation
7
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS
6, 8
Bandwidth –3 dB
Total Harmonic Distortion
V
W
Settling Time (10 kΩ/50 kΩ/100 kΩ)
Resistor Noise Voltage Density
1
2
Symbol
Conditions
Min
Typ
1
Max
Unit
R-DNL
R-INL
∆R
AB
∆R
AB
/∆T
R
W
N
DNL
INL
∆V
W
/∆T
V
WFSE
V
WZSE
V
A,B,W
C
A,B
C
W
I
CM
V
IH
V
IL
V
IH
V
IL
I
IL
C
IL
V
DD RANGE
I
DD
P
DISS
PSS
BW
THD
W
t
S
e
N_WB
R
WB
, V
A
= no connect
R
WB
, V
A
= no connect
T
A
= 25°C
V
AB
= V
DD
,
Wiper = no connect
V
DD
= 5 V
Specifications apply to all VRs
−1
−2
−15
±0.1
±0.25
45
50
+1
+2
+15
LSB
LSB
%
ppm/°C
Ω
Bits
LSB
LSB
ppm/°C
LSB
LSB
V
pF
pF
nA
V
V
V
V
μA
pF
V
μA
mW
%/%
kHz
%
μs
nV/√Hz
120
8
+1
+1
−1
−1
Code = 0x80
Code = 0xFF
Code = 0x00
−3
0
GND
f = 1 MHz, measured to GND, code =
0x80
f = 1 MHz, measured to GND, code =
0x80
V
A
= V
B
= V
DD
/2
2.4
±0.1
±0.3
15
−1
1
0
3
V
DD
45
60
1
0.8
V
DD
= 3 V
V
DD
= 3 V
V
IN
= 0 V or 5 V
2.1
0.6
±1
5
2.7
V
IH
= 5 V or V
IL
= 0 V
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
∆V
DD
= +5 V ± 10%, code = midscale
R
AB
= 10 kΩ/50 kΩ/100 kΩ, Code = 0x80
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz, R
AB
=
10 kΩ
V
A
= 5 V, V
B
= 0 V,
±1 LSB error band
R
WB
= 5 kΩ
3
±0.02
600/100/40
0.05
2
9
5.5
8
0.2
±0.05
Typical specifications represent average readings at +25°C and V
DD
= 5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter (DAC). V
A
= V
DD
and V
B
=
0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
× V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
Rev. B | Page 4 of 16
AD5160
TIMING CHARACTERISTICS—ALL VERSIONS
V
DD
= +5V ± 10%, or +3V ± 10%; V
A
= V
DD
; V
B
= 0 V; –40°C < T
A
< +125°C; unless otherwise noted.
Table 3.
Parameter
SPI INTERFACE TIMING CHARACTERISTICS
1, 2
Clock Frequency
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
1
Symbol
f
CLK
t
CH
, t
CL
t
DS
t
DH
t
CSS
t
CSW
t
CSH0
t
CSH1
Conditions
Specifications apply to all parts
Clock level high or low
Min
Typ
1
Max
25
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
20
5
5
15
40
0
0
See the timing diagram, Figure 38, for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a
voltage level of 1.5 V.
2
Guaranteed by design and not subject to production test.
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